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coresight: Add label sysfs node support

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For some coresight components like CTI and TPDM, there could be
numerous of them. From the node name, we can only get the type and
register address of the component. We can't identify the HW or the
system the component belongs to. Add label sysfs node support for
showing the intuitive name of the device.

Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250816072529.3716968-3-quic_jinlmao@quicinc.com
This commit is contained in:
Mao Jinlong 2025-08-16 00:25:29 -07:00 committed by Suzuki K Poulose
parent 1ad38ef4db
commit 01f96b8125
11 changed files with 129 additions and 2 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

6
Documentation/ABI/testing/sysfs-bus-coresight-devices-cti
View file

@ -239,3 +239,9 @@ Date: March 2020
KernelVersion: 5.7
Contact: Mike Leach or Mathieu Poirier
Description: (Write) Clear all channel / trigger programming.
What: /sys/bus/coresight/devices/<cti-name>/label
Date: Aug 2025
KernelVersion 6.18
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
Description: (Read) Show hardware context information of device.

6
Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source
View file

@ -13,3 +13,9 @@ KernelVersion: 6.14
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
Description: (R) Show the trace ID that will appear in the trace stream
coming from this trace entity.
What: /sys/bus/coresight/devices/dummy_source<N>/label
Date: Aug 2025
KernelVersion 6.18
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
Description: (Read) Show hardware context information of device.

6
Documentation/ABI/testing/sysfs-bus-coresight-devices-etb10
View file

@ -19,6 +19,12 @@ Description: (RW) Disables write access to the Trace RAM by stopping the
into the Trace RAM following the trigger event is equal to the
value stored in this register+1 (from ARM ETB-TRM).
What: /sys/bus/coresight/devices/<memory_map>.etb/label
Date: Aug 2025
KernelVersion 6.18
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
Description: (Read) Show hardware context information of device.
What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp
Date: March 2016
KernelVersion: 4.7

6
Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x
View file

@ -251,6 +251,12 @@ KernelVersion: 4.4
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
Description: (RO) Holds the cpu number this tracer is affined to.
What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/label
Date: Aug 2025
KernelVersion 6.18
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
Description: (Read) Show hardware context information of device.
What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmccr
Date: September 2015
KernelVersion: 4.4

6
Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
View file

@ -329,6 +329,12 @@ Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
Description: (RW) Access the selected single show PE comparator control
register.
What: /sys/bus/coresight/devices/etm<N>/label
Date: Aug 2025
KernelVersion 6.18
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
Description: (Read) Show hardware context information of device.
What: /sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr
Date: April 2015
KernelVersion: 4.01

6
Documentation/ABI/testing/sysfs-bus-coresight-devices-funnel
View file

@ -10,3 +10,9 @@ Date: November 2014
KernelVersion: 3.19
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
Description: (RW) Defines input port priority order.
What: /sys/bus/coresight/devices/<memory_map>.funnel/label
Date: Aug 2025
KernelVersion 6.18
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
Description: (Read) Show hardware context information of device.

6
Documentation/ABI/testing/sysfs-bus-coresight-devices-stm
View file

@ -51,3 +51,9 @@ KernelVersion: 4.7
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
Description: (RW) Holds the trace ID that will appear in the trace stream
coming from this trace entity.
What: /sys/bus/coresight/devices/<memory_map>.stm/label
Date: Aug 2025
KernelVersion 6.18
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
Description: (Read) Show hardware context information of device.

6
Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc
View file

@ -107,3 +107,9 @@ Contact: Anshuman Khandual <anshuman.khandual@arm.com>
Description: (RW) Current Coresight TMC-ETR buffer mode selected. But user could
only provide a mode which is supported for a given ETR device. This
file is available only for TMC ETR devices.
What: /sys/bus/coresight/devices/<memory_map>.tmc/label
Date: Aug 2025
KernelVersion 6.18
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
Description: (Read) Show hardware context information of device.

6
Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
View file

@ -272,3 +272,9 @@ KernelVersion 6.15
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Description:
(RW) Set/Get the enablement of the individual lane.
What: /sys/bus/coresight/devices/<tpdm-name>/label
Date: Aug 2025
KernelVersion 6.18
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
Description: (Read) Show hardware context information of device.

6
Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe
View file

@ -12,3 +12,9 @@ Contact: Anshuman Khandual <anshuman.khandual@arm.com>
Description: (Read) Shows if TRBE updates in the memory are with access
and dirty flag updates as well. This value is fetched from
the TRBIDR register.
What: /sys/bus/coresight/devices/trbe<cpu>/label
Date: Aug 2025
KernelVersion 6.18
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
Description: (Read) Show hardware context information of device.

71
drivers/hwtracing/coresight/coresight-sysfs.c
View file

@ -7,6 +7,7 @@
#include <linux/device.h>
#include <linux/idr.h>
#include <linux/kernel.h>
#include <linux/property.h>
#include "coresight-priv.h"
#include "coresight-trace-id.h"
@ -371,17 +372,81 @@ static ssize_t enable_source_store(struct device *dev,
}
static DEVICE_ATTR_RW(enable_source);
static ssize_t label_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
const char *str;
int ret;
ret = fwnode_property_read_string(dev_fwnode(dev), "label", &str);
if (ret == 0)
return sysfs_emit(buf, "%s\n", str);
else
return ret;
}
static DEVICE_ATTR_RO(label);
static umode_t label_is_visible(struct kobject *kobj,
struct attribute *attr, int n)
{
struct device *dev = kobj_to_dev(kobj);
if (attr == &dev_attr_label.attr) {
if (fwnode_property_present(dev_fwnode(dev), "label"))
return attr->mode;
else
return 0;
}
return attr->mode;
}
static struct attribute *coresight_sink_attrs[] = {
&dev_attr_enable_sink.attr,
&dev_attr_label.attr,
NULL,
};
ATTRIBUTE_GROUPS(coresight_sink);
static struct attribute_group coresight_sink_group = {
.attrs = coresight_sink_attrs,
.is_visible = label_is_visible,
};
__ATTRIBUTE_GROUPS(coresight_sink);
static struct attribute *coresight_source_attrs[] = {
&dev_attr_enable_source.attr,
&dev_attr_label.attr,
NULL,
};
ATTRIBUTE_GROUPS(coresight_source);
static struct attribute_group coresight_source_group = {
.attrs = coresight_source_attrs,
.is_visible = label_is_visible,
};
__ATTRIBUTE_GROUPS(coresight_source);
static struct attribute *coresight_link_attrs[] = {
&dev_attr_label.attr,
NULL,
};
static struct attribute_group coresight_link_group = {
.attrs = coresight_link_attrs,
.is_visible = label_is_visible,
};
__ATTRIBUTE_GROUPS(coresight_link);
static struct attribute *coresight_helper_attrs[] = {
&dev_attr_label.attr,
NULL,
};
static struct attribute_group coresight_helper_group = {
.attrs = coresight_helper_attrs,
.is_visible = label_is_visible,
};
__ATTRIBUTE_GROUPS(coresight_helper);
const struct device_type coresight_dev_type[] = {
[CORESIGHT_DEV_TYPE_SINK] = {
@ -390,6 +455,7 @@ const struct device_type coresight_dev_type[] = {
},
[CORESIGHT_DEV_TYPE_LINK] = {
.name = "link",
.groups = coresight_link_groups,
},
[CORESIGHT_DEV_TYPE_LINKSINK] = {
.name = "linksink",
@ -401,6 +467,7 @@ const struct device_type coresight_dev_type[] = {
},
[CORESIGHT_DEV_TYPE_HELPER] = {
.name = "helper",
.groups = coresight_helper_groups,
}
};
/* Ensure the enum matches the names and groups */