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spi: add driver for ar934x spi controller
This patch adds driver for SPI controller found in Qualcomm Atheros AR934x/QCA95xx SoCs. This controller is a superset of the already supported qca,ar7100-spi. Besides the bit-bang mode in spi-ath79.c, this new controller added a new "shift register" mode, allowing faster spi operations. Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Link: https://lore.kernel.org/r/20200210034152.49063-2-gch981213@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Chuanhong Guo
Mark Brown
parent
4a08d6c866
commit
047980c582
3 changed files with 243 additions and 0 deletions
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@ -62,6 +62,13 @@ config SPI_ALTERA
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help
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This is the driver for the Altera SPI Controller.
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config SPI_AR934X
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tristate "Qualcomm Atheros AR934X/QCA95XX SPI controller driver"
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depends on ATH79 || COMPILE_TEST
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help
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This enables support for the SPI controller present on the
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Qualcomm Atheros AR934X/QCA95XX SoCs.
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config SPI_ATH79
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tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
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depends on ATH79 || COMPILE_TEST
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@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
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# SPI master controller drivers (bus)
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obj-$(CONFIG_SPI_ALTERA) += spi-altera.o
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obj-$(CONFIG_SPI_AR934X) += spi-ar934x.o
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obj-$(CONFIG_SPI_ARMADA_3700) += spi-armada-3700.o
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obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
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obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o
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235
drivers/spi/spi-ar934x.c
Normal file
235
drivers/spi/spi-ar934x.c
Normal file
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@ -0,0 +1,235 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
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//
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// Copyright (C) 2020 Chuanhong Guo <gch981213@gmail.com>
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//
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// Based on spi-mt7621.c:
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// Copyright (C) 2011 Sergiy <piratfm@gmail.com>
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// Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
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// Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/spi/spi.h>
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#define DRIVER_NAME "spi-ar934x"
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#define AR934X_SPI_REG_FS 0x00
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#define AR934X_SPI_ENABLE BIT(0)
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#define AR934X_SPI_REG_IOC 0x08
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#define AR934X_SPI_IOC_INITVAL 0x70000
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#define AR934X_SPI_REG_CTRL 0x04
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#define AR934X_SPI_CLK_MASK GENMASK(5, 0)
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#define AR934X_SPI_DATAOUT 0x10
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#define AR934X_SPI_REG_SHIFT_CTRL 0x14
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#define AR934X_SPI_SHIFT_EN BIT(31)
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#define AR934X_SPI_SHIFT_CS(n) BIT(28 + (n))
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#define AR934X_SPI_SHIFT_TERM 26
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#define AR934X_SPI_SHIFT_VAL(cs, term, count) \
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(AR934X_SPI_SHIFT_EN | AR934X_SPI_SHIFT_CS(cs) | \
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(term) << AR934X_SPI_SHIFT_TERM | (count))
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#define AR934X_SPI_DATAIN 0x18
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struct ar934x_spi {
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struct spi_controller *ctlr;
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void __iomem *base;
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struct clk *clk;
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unsigned int clk_freq;
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};
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static inline int ar934x_spi_clk_div(struct ar934x_spi *sp, unsigned int freq)
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{
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int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1;
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if (div < 0)
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return 0;
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else if (div > AR934X_SPI_CLK_MASK)
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return -EINVAL;
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else
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return div;
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}
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static int ar934x_spi_setup(struct spi_device *spi)
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{
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struct ar934x_spi *sp = spi_controller_get_devdata(spi->master);
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if ((spi->max_speed_hz == 0) ||
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(spi->max_speed_hz > (sp->clk_freq / 2))) {
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spi->max_speed_hz = sp->clk_freq / 2;
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} else if (spi->max_speed_hz < (sp->clk_freq / 128)) {
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dev_err(&spi->dev, "spi clock is too low\n");
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return -EINVAL;
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}
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return 0;
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}
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static int ar934x_spi_transfer_one_message(struct spi_controller *master,
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struct spi_message *m)
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{
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struct ar934x_spi *sp = spi_controller_get_devdata(master);
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struct spi_transfer *t = NULL;
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struct spi_device *spi = m->spi;
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unsigned long trx_done, trx_cur;
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int stat = 0;
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u8 term = 0;
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int div, i;
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u32 reg;
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const u8 *tx_buf;
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u8 *buf;
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m->actual_length = 0;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (t->speed_hz)
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div = ar934x_spi_clk_div(sp, t->speed_hz);
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else
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div = ar934x_spi_clk_div(sp, spi->max_speed_hz);
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if (div < 0) {
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stat = -EIO;
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goto msg_done;
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}
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reg = ioread32(sp->base + AR934X_SPI_REG_CTRL);
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reg &= ~AR934X_SPI_CLK_MASK;
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reg |= div;
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iowrite32(reg, sp->base + AR934X_SPI_REG_CTRL);
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iowrite32(0, sp->base + AR934X_SPI_DATAOUT);
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for (trx_done = 0; trx_done < t->len; trx_done += 4) {
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trx_cur = t->len - trx_done;
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if (trx_cur > 4)
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trx_cur = 4;
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else if (list_is_last(&t->transfer_list, &m->transfers))
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term = 1;
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if (t->tx_buf) {
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tx_buf = t->tx_buf + trx_done;
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reg = tx_buf[0];
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for (i = 1; i < trx_cur; i++)
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reg = reg << 8 | tx_buf[i];
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iowrite32(reg, sp->base + AR934X_SPI_DATAOUT);
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}
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reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term,
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trx_cur * 8);
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iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL);
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stat = readl_poll_timeout(
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sp->base + AR934X_SPI_REG_SHIFT_CTRL, reg,
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!(reg & AR934X_SPI_SHIFT_EN), 0, 5);
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if (stat < 0)
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goto msg_done;
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if (t->rx_buf) {
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reg = ioread32(sp->base + AR934X_SPI_DATAIN);
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buf = t->rx_buf + trx_done;
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for (i = 0; i < trx_cur; i++) {
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buf[trx_cur - i - 1] = reg & 0xff;
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reg >>= 8;
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}
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}
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}
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m->actual_length += t->len;
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}
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msg_done:
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m->status = stat;
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spi_finalize_current_message(master);
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return 0;
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}
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static const struct of_device_id ar934x_spi_match[] = {
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{ .compatible = "qca,ar934x-spi" },
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{},
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};
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MODULE_DEVICE_TABLE(of, ar934x_spi_match);
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static int ar934x_spi_probe(struct platform_device *pdev)
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{
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struct spi_controller *ctlr;
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struct ar934x_spi *sp;
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void __iomem *base;
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struct clk *clk;
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int ret;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "failed to get clock\n");
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return PTR_ERR(clk);
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}
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ret = clk_prepare_enable(clk);
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if (ret)
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return ret;
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ctlr = spi_alloc_master(&pdev->dev, sizeof(*sp));
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if (!ctlr) {
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dev_info(&pdev->dev, "failed to allocate spi controller\n");
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return -ENOMEM;
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}
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/* disable flash mapping and expose spi controller registers */
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iowrite32(AR934X_SPI_ENABLE, base + AR934X_SPI_REG_FS);
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/* restore pins to default state: CSn=1 DO=CLK=0 */
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iowrite32(AR934X_SPI_IOC_INITVAL, base + AR934X_SPI_REG_IOC);
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ctlr->mode_bits = SPI_LSB_FIRST;
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ctlr->setup = ar934x_spi_setup;
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ctlr->transfer_one_message = ar934x_spi_transfer_one_message;
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ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
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ctlr->dev.of_node = pdev->dev.of_node;
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ctlr->num_chipselect = 3;
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dev_set_drvdata(&pdev->dev, ctlr);
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sp = spi_controller_get_devdata(ctlr);
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sp->base = base;
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sp->clk = clk;
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sp->clk_freq = clk_get_rate(clk);
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sp->ctlr = ctlr;
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return devm_spi_register_controller(&pdev->dev, ctlr);
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}
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static int ar934x_spi_remove(struct platform_device *pdev)
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{
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struct spi_controller *ctlr;
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struct ar934x_spi *sp;
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ctlr = dev_get_drvdata(&pdev->dev);
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sp = spi_controller_get_devdata(ctlr);
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clk_disable_unprepare(sp->clk);
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return 0;
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}
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static struct platform_driver ar934x_spi_driver = {
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.driver = {
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.name = DRIVER_NAME,
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.of_match_table = ar934x_spi_match,
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},
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.probe = ar934x_spi_probe,
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.remove = ar934x_spi_remove,
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};
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module_platform_driver(ar934x_spi_driver);
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MODULE_DESCRIPTION("SPI controller driver for Qualcomm Atheros AR934x/QCA95xx");
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MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:" DRIVER_NAME);
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