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net: pcs: rzn1-miic: Add RZ/T2H MIIC support

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Add support for the Renesas RZ/T2H MIIC by defining SoC-specific
modctrl match tables, register map, and string representations
for converters and ports.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://patch.msgid.link/20250910204132.319975-10-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Lad Prabhakar 2025-09-10 21:41:30 +01:00 committed by Jakub Kicinski
parent 419747319e
commit 08f89e4212
2 changed files with 88 additions and 5 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

11
drivers/net/pcs/Kconfig
View file

@ -26,11 +26,12 @@ config PCS_MTK_LYNXI
which is part of MediaTek's SoC and Ethernet switch ICs.
config PCS_RZN1_MIIC
tristate "Renesas RZ/N1 MII converter"
depends on OF && (ARCH_RZN1 || COMPILE_TEST)
tristate "Renesas RZ/N1, RZ/N2H, RZ/T2H MII converter"
depends on OF
depends on ARCH_RZN1 || ARCH_R9A09G077 || ARCH_R9A09G087 || COMPILE_TEST
help
This module provides a driver for the MII converter that is available
on RZ/N1 SoCs. This PCS converts MII to RMII/RGMII or can be set in
pass-through mode for MII.
This module provides a driver for the MII converter available on
Renesas RZ/N1, RZ/N2H, and RZ/T2H SoCs. This PCS converts MII to
RMII/RGMII, or can be set in pass-through mode for MII.
endmenu

82
drivers/net/pcs/pcs-rzn1-miic.c
View file

@ -21,6 +21,7 @@
#include <linux/reset.h>
#include <linux/slab.h>
#include <dt-bindings/net/pcs-rzn1-miic.h>
#include <dt-bindings/net/renesas,r9a09g077-pcs-miic.h>
#define MIIC_PRCMD 0x0
#define MIIC_ESID_CODE 0x4
@ -125,6 +126,57 @@ static const char * const index_to_string[] = {
"CONV5",
};
static struct modctrl_match rzt2h_modctrl_match_table[] = {
{0x0, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ETHSW_PORT1,
ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}},
{0x1, {MIIC_MODCTRL_CONF_NONE, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1,
ETHSS_GMAC2_PORT, ETHSS_GMAC1_PORT}},
{0x2, {ETHSS_GMAC0_PORT, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1,
ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}},
{0x3, {MIIC_MODCTRL_CONF_NONE, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1,
ETHSS_ESC_PORT2, ETHSS_GMAC1_PORT}},
{0x4, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ESC_PORT1,
ETHSS_ESC_PORT2, ETHSS_GMAC1_PORT}},
{0x5, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ESC_PORT1,
ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}},
{0x6, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ETHSW_PORT1,
ETHSS_GMAC2_PORT, ETHSS_GMAC1_PORT}},
{0x7, {MIIC_MODCTRL_CONF_NONE, ETHSS_GMAC0_PORT, ETHSS_GMAC1_PORT,
ETHSS_GMAC2_PORT, MIIC_MODCTRL_CONF_NONE}}
};
static const char * const rzt2h_conf_to_string[] = {
[ETHSS_GMAC0_PORT] = "GMAC0_PORT",
[ETHSS_GMAC1_PORT] = "GMAC1_PORT",
[ETHSS_GMAC2_PORT] = "GMAC2_PORT",
[ETHSS_ESC_PORT0] = "ETHERCAT_PORT0",
[ETHSS_ESC_PORT1] = "ETHERCAT_PORT1",
[ETHSS_ESC_PORT2] = "ETHERCAT_PORT2",
[ETHSS_ETHSW_PORT0] = "SWITCH_PORT0",
[ETHSS_ETHSW_PORT1] = "SWITCH_PORT1",
[ETHSS_ETHSW_PORT2] = "SWITCH_PORT2",
};
static const char * const rzt2h_index_to_string[] = {
"SWITCH_PORTIN",
"CONV0",
"CONV1",
"CONV2",
"CONV3",
};
static const char * const rzt2h_reset_ids[] = {
"rst",
"crst",
};
/**
* struct miic - MII converter structure
* @base: base address of the MII converter
@ -204,11 +256,24 @@ static void miic_unlock_regs(struct miic *miic)
writel(0x0001, miic->base + MIIC_PRCMD);
}
static void miic_lock_regs(struct miic *miic)
{
/* Protect register writes */
writel(0x0000, miic->base + MIIC_PRCMD);
}
static void miic_reg_writel_unlocked(struct miic *miic, int offset, u32 value)
{
writel(value, miic->base + offset);
}
static void miic_reg_writel_locked(struct miic *miic, int offset, u32 value)
{
miic_unlock_regs(miic);
writel(value, miic->base + offset);
miic_lock_regs(miic);
}
static void miic_reg_writel(struct miic *miic, int offset, u32 value)
{
miic->of_data->miic_write(miic, offset, value);
@ -666,7 +731,24 @@ static struct miic_of_data rzn1_miic_of_data = {
.miic_write = miic_reg_writel_unlocked,
};
static struct miic_of_data rzt2h_miic_of_data = {
.match_table = rzt2h_modctrl_match_table,
.match_table_count = ARRAY_SIZE(rzt2h_modctrl_match_table),
.conf_conv_count = 5,
.conf_to_string = rzt2h_conf_to_string,
.conf_to_string_count = ARRAY_SIZE(rzt2h_conf_to_string),
.index_to_string = rzt2h_index_to_string,
.index_to_string_count = ARRAY_SIZE(rzt2h_index_to_string),
.miic_port_start = 0,
.miic_port_max = 4,
.sw_mode_mask = GENMASK(2, 0),
.reset_ids = rzt2h_reset_ids,
.reset_count = ARRAY_SIZE(rzt2h_reset_ids),
.miic_write = miic_reg_writel_locked,
};
static const struct of_device_id miic_of_mtable[] = {
{ .compatible = "renesas,r9a09g077-miic", .data = &rzt2h_miic_of_data },
{ .compatible = "renesas,rzn1-miic", .data = &rzn1_miic_of_data },
{ /* sentinel */ }
};