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x86/pci: Clean up open-coded PCIBIOS return code mangling
Per PCI Firmware spec r3.3, sec 2.5.2, 2.6.2, and 2.7, the return code for these PCI BIOS interfaces is in 8 bits of the EAX register. Previously it was extracted by open-coded masks and shifting. Name the return code bits with a #define and add pcibios_get_return_code() to extract the return code to improve code readability. In addition, replace zero test with PCIBIOS_SUCCESSFUL. No functional changes intended. Link: https://lore.kernel.org/r/20231124085924.13830-1-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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1 changed files with 21 additions and 7 deletions
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@ -3,6 +3,8 @@
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* BIOS32 and PCI BIOS handling.
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* BIOS32 and PCI BIOS handling.
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*/
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*/
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#include <linux/bits.h>
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#include <linux/bitfield.h>
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#include <linux/pci.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/slab.h>
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@ -29,8 +31,19 @@
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#define PCIBIOS_HW_TYPE1_SPEC 0x10
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#define PCIBIOS_HW_TYPE1_SPEC 0x10
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#define PCIBIOS_HW_TYPE2_SPEC 0x20
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#define PCIBIOS_HW_TYPE2_SPEC 0x20
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/*
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* Returned in EAX:
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* - AH: return code
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*/
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#define PCIBIOS_RETURN_CODE GENMASK(15, 8)
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int pcibios_enabled;
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int pcibios_enabled;
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static u8 pcibios_get_return_code(u32 eax)
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{
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return FIELD_GET(PCIBIOS_RETURN_CODE, eax);
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}
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/* According to the BIOS specification at:
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/* According to the BIOS specification at:
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* http://members.datafast.net.au/dft0802/specs/bios21.pdf, we could
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* http://members.datafast.net.au/dft0802/specs/bios21.pdf, we could
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* restrict the x zone to some pages and make it ro. But this may be
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* restrict the x zone to some pages and make it ro. But this may be
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@ -154,7 +167,7 @@ static int __init check_pcibios(void)
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: "memory");
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: "memory");
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local_irq_restore(flags);
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local_irq_restore(flags);
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status = (eax >> 8) & 0xff;
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status = pcibios_get_return_code(eax);
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hw_mech = eax & 0xff;
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hw_mech = eax & 0xff;
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major_ver = (ebx >> 8) & 0xff;
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major_ver = (ebx >> 8) & 0xff;
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minor_ver = ebx & 0xff;
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minor_ver = ebx & 0xff;
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@ -227,7 +240,7 @@ static int pci_bios_read(unsigned int seg, unsigned int bus,
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raw_spin_unlock_irqrestore(&pci_config_lock, flags);
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raw_spin_unlock_irqrestore(&pci_config_lock, flags);
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return (int)((result & 0xff00) >> 8);
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return pcibios_get_return_code(result);
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}
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}
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static int pci_bios_write(unsigned int seg, unsigned int bus,
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static int pci_bios_write(unsigned int seg, unsigned int bus,
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@ -269,7 +282,7 @@ static int pci_bios_write(unsigned int seg, unsigned int bus,
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raw_spin_unlock_irqrestore(&pci_config_lock, flags);
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raw_spin_unlock_irqrestore(&pci_config_lock, flags);
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return (int)((result & 0xff00) >> 8);
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return pcibios_get_return_code(result);
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}
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}
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@ -385,9 +398,10 @@ struct irq_routing_table * pcibios_get_irq_routing_table(void)
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"m" (opt)
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"m" (opt)
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: "memory");
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: "memory");
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DBG("OK ret=%d, size=%d, map=%x\n", ret, opt.size, map);
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DBG("OK ret=%d, size=%d, map=%x\n", ret, opt.size, map);
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if (ret & 0xff00)
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ret = pcibios_get_return_code(ret);
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printk(KERN_ERR "PCI: Error %02x when fetching IRQ routing table.\n", (ret >> 8) & 0xff);
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if (ret) {
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else if (opt.size) {
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printk(KERN_ERR "PCI: Error %02x when fetching IRQ routing table.\n", ret);
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} else if (opt.size) {
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rt = kmalloc(sizeof(struct irq_routing_table) + opt.size, GFP_KERNEL);
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rt = kmalloc(sizeof(struct irq_routing_table) + opt.size, GFP_KERNEL);
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if (rt) {
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if (rt) {
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memset(rt, 0, sizeof(struct irq_routing_table));
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memset(rt, 0, sizeof(struct irq_routing_table));
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@ -415,7 +429,7 @@ int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq)
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"b" ((dev->bus->number << 8) | dev->devfn),
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"b" ((dev->bus->number << 8) | dev->devfn),
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"c" ((irq << 8) | (pin + 10)),
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"c" ((irq << 8) | (pin + 10)),
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"S" (&pci_indirect));
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"S" (&pci_indirect));
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return !(ret & 0xff00);
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return pcibios_get_return_code(ret) == PCIBIOS_SUCCESSFUL;
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}
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}
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EXPORT_SYMBOL(pcibios_set_irq_routing);
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EXPORT_SYMBOL(pcibios_set_irq_routing);
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