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clk: zynq: Add clock controller driver
Add a clock controller driver and documentation. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Rob Landley <rob@landley.net> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-doc@vger.kernel.org Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Soren Brinkmann
Michal Simek
parent
3682af46d5
commit
0ee52b157b
2 changed files with 630 additions and 0 deletions
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@ -6,6 +6,103 @@ The purpose of this document is to document their usage.
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See clock_bindings.txt for more information on the generic clock bindings.
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See Chapter 25 of Zynq TRM for more information about Zynq clocks.
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== Clock Controller ==
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The clock controller is a logical abstraction of Zynq's clock tree. It reads
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required input clock frequencies from the devicetree and acts as clock provider
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for all clock consumers of PS clocks.
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Required properties:
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- #clock-cells : Must be 1
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- compatible : "xlnx,ps7-clkc"
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- ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
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(usually 33 MHz oscillators are used for Zynq platforms)
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- clock-output-names : List of strings used to name the clock outputs. Shall be
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a list of the outputs given below.
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Optional properties:
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- clocks : as described in the clock bindings
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- clock-names : as described in the clock bindings
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Clock inputs:
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The following strings are optional parameters to the 'clock-names' property in
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order to provide an optional (E)MIO clock source.
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- swdt_ext_clk
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- gem0_emio_clk
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- gem1_emio_clk
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- mio_clk_XX # with XX = 00..53
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...
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Clock outputs:
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0: armpll
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1: ddrpll
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2: iopll
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3: cpu_6or4x
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4: cpu_3or2x
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5: cpu_2x
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6: cpu_1x
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7: ddr2x
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8: ddr3x
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9: dci
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10: lqspi
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11: smc
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12: pcap
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13: gem0
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14: gem1
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15: fclk0
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16: fclk1
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17: fclk2
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18: fclk3
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19: can0
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20: can1
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21: sdio0
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22: sdio1
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23: uart0
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24: uart1
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25: spi0
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26: spi1
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27: dma
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28: usb0_aper
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29: usb1_aper
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30: gem0_aper
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31: gem1_aper
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32: sdio0_aper
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33: sdio1_aper
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34: spi0_aper
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35: spi1_aper
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36: can0_aper
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37: can1_aper
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38: i2c0_aper
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39: i2c1_aper
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40: uart0_aper
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41: uart1_aper
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42: gpio_aper
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43: lqspi_aper
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44: smc_aper
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45: swdt
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46: dbg_trc
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47: dbg_apb
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Example:
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clkc: clkc {
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#clock-cells = <1>;
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compatible = "xlnx,ps7-clkc";
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ps-clk-frequency = <33333333>;
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clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
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"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
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"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
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"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
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"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
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"dma", "usb0_aper", "usb1_aper", "gem0_aper",
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"gem1_aper", "sdio0_aper", "sdio1_aper",
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"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
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"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
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"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
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"dbg_trc", "dbg_apb";
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# optional props
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clocks = <&clkc 16>, <&clk_foo>;
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clock-names = "gem1_emio_clk", "can_mio_clk_23";
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};
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== PLLs ==
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Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
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533
drivers/clk/zynq/clkc.c
Normal file
533
drivers/clk/zynq/clkc.c
Normal file
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@ -0,0 +1,533 @@
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/*
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* Zynq clock controller
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*
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* Copyright (C) 2012 - 2013 Xilinx
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*
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* Sören Brinkmann <soren.brinkmann@xilinx.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License v2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk/zynq.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/io.h>
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static void __iomem *zynq_slcr_base_priv;
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#define SLCR_ARMPLL_CTRL (zynq_slcr_base_priv + 0x100)
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#define SLCR_DDRPLL_CTRL (zynq_slcr_base_priv + 0x104)
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#define SLCR_IOPLL_CTRL (zynq_slcr_base_priv + 0x108)
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#define SLCR_PLL_STATUS (zynq_slcr_base_priv + 0x10c)
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#define SLCR_ARM_CLK_CTRL (zynq_slcr_base_priv + 0x120)
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#define SLCR_DDR_CLK_CTRL (zynq_slcr_base_priv + 0x124)
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#define SLCR_DCI_CLK_CTRL (zynq_slcr_base_priv + 0x128)
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#define SLCR_APER_CLK_CTRL (zynq_slcr_base_priv + 0x12c)
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#define SLCR_GEM0_CLK_CTRL (zynq_slcr_base_priv + 0x140)
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#define SLCR_GEM1_CLK_CTRL (zynq_slcr_base_priv + 0x144)
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#define SLCR_SMC_CLK_CTRL (zynq_slcr_base_priv + 0x148)
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#define SLCR_LQSPI_CLK_CTRL (zynq_slcr_base_priv + 0x14c)
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#define SLCR_SDIO_CLK_CTRL (zynq_slcr_base_priv + 0x150)
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#define SLCR_UART_CLK_CTRL (zynq_slcr_base_priv + 0x154)
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#define SLCR_SPI_CLK_CTRL (zynq_slcr_base_priv + 0x158)
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#define SLCR_CAN_CLK_CTRL (zynq_slcr_base_priv + 0x15c)
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#define SLCR_CAN_MIOCLK_CTRL (zynq_slcr_base_priv + 0x160)
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#define SLCR_DBG_CLK_CTRL (zynq_slcr_base_priv + 0x164)
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#define SLCR_PCAP_CLK_CTRL (zynq_slcr_base_priv + 0x168)
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#define SLCR_FPGA0_CLK_CTRL (zynq_slcr_base_priv + 0x170)
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#define SLCR_621_TRUE (zynq_slcr_base_priv + 0x1c4)
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#define SLCR_SWDT_CLK_SEL (zynq_slcr_base_priv + 0x304)
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#define NUM_MIO_PINS 54
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enum zynq_clk {
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armpll, ddrpll, iopll,
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cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
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ddr2x, ddr3x, dci,
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lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,
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sdio0, sdio1, uart0, uart1, spi0, spi1, dma,
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usb0_aper, usb1_aper, gem0_aper, gem1_aper,
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sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper,
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i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper,
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smc_aper, swdt, dbg_trc, dbg_apb, clk_max};
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static struct clk *ps_clk;
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static struct clk *clks[clk_max];
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static struct clk_onecell_data clk_data;
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static DEFINE_SPINLOCK(armpll_lock);
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static DEFINE_SPINLOCK(ddrpll_lock);
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static DEFINE_SPINLOCK(iopll_lock);
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static DEFINE_SPINLOCK(armclk_lock);
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static DEFINE_SPINLOCK(ddrclk_lock);
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static DEFINE_SPINLOCK(dciclk_lock);
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static DEFINE_SPINLOCK(gem0clk_lock);
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static DEFINE_SPINLOCK(gem1clk_lock);
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static DEFINE_SPINLOCK(canclk_lock);
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static DEFINE_SPINLOCK(canmioclk_lock);
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static DEFINE_SPINLOCK(dbgclk_lock);
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static DEFINE_SPINLOCK(aperclk_lock);
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static const char dummy_nm[] __initconst = "dummy_name";
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static const char *armpll_parents[] __initdata = {"armpll_int", "ps_clk"};
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static const char *ddrpll_parents[] __initdata = {"ddrpll_int", "ps_clk"};
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static const char *iopll_parents[] __initdata = {"iopll_int", "ps_clk"};
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static const char *gem0_mux_parents[] __initdata = {"gem0_div1", dummy_nm};
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static const char *gem1_mux_parents[] __initdata = {"gem1_div1", dummy_nm};
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static const char *can0_mio_mux2_parents[] __initdata = {"can0_gate",
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"can0_mio_mux"};
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static const char *can1_mio_mux2_parents[] __initdata = {"can1_gate",
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"can1_mio_mux"};
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static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div",
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dummy_nm};
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static const char *dbgtrc_emio_input_names[] __initdata = {"trace_emio_clk"};
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static const char *gem0_emio_input_names[] __initdata = {"gem0_emio_clk"};
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static const char *gem1_emio_input_names[] __initdata = {"gem1_emio_clk"};
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static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"};
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static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
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const char *clk_name, void __iomem *fclk_ctrl_reg,
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const char **parents)
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{
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struct clk *clk;
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char *mux_name;
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char *div0_name;
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char *div1_name;
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spinlock_t *fclk_lock;
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spinlock_t *fclk_gate_lock;
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void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8;
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fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL);
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if (!fclk_lock)
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goto err;
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fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL);
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if (!fclk_gate_lock)
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goto err;
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spin_lock_init(fclk_lock);
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spin_lock_init(fclk_gate_lock);
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mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name);
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div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
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div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
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clk = clk_register_mux(NULL, mux_name, parents, 4, 0,
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fclk_ctrl_reg, 4, 2, 0, fclk_lock);
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clk = clk_register_divider(NULL, div0_name, mux_name,
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0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
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clk = clk_register_divider(NULL, div1_name, div0_name,
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CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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fclk_lock);
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clks[fclk] = clk_register_gate(NULL, clk_name,
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div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
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0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
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kfree(mux_name);
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kfree(div0_name);
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kfree(div1_name);
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return;
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err:
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clks[fclk] = ERR_PTR(-ENOMEM);
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}
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static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
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enum zynq_clk clk1, const char *clk_name0,
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const char *clk_name1, void __iomem *clk_ctrl,
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const char **parents, unsigned int two_gates)
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{
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struct clk *clk;
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char *mux_name;
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char *div_name;
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spinlock_t *lock;
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lock = kmalloc(sizeof(*lock), GFP_KERNEL);
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if (!lock)
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goto err;
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spin_lock_init(lock);
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mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
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div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
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clk = clk_register_mux(NULL, mux_name, parents, 4, 0,
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clk_ctrl, 4, 2, 0, lock);
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clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
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clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
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CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);
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if (two_gates)
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clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,
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CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);
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kfree(mux_name);
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kfree(div_name);
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return;
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err:
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clks[clk0] = ERR_PTR(-ENOMEM);
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if (two_gates)
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clks[clk1] = ERR_PTR(-ENOMEM);
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}
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static void __init zynq_clk_setup(struct device_node *np)
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{
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int i;
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u32 tmp;
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int ret;
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struct clk *clk;
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char *clk_name;
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const char *clk_output_name[clk_max];
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const char *cpu_parents[4];
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const char *periph_parents[4];
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const char *swdt_ext_clk_mux_parents[2];
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const char *can_mio_mux_parents[NUM_MIO_PINS];
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pr_info("Zynq clock init\n");
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/* get clock output names from DT */
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for (i = 0; i < clk_max; i++) {
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if (of_property_read_string_index(np, "clock-output-names",
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i, &clk_output_name[i])) {
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pr_err("%s: clock output name not in DT\n", __func__);
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BUG();
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}
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}
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cpu_parents[0] = clk_output_name[armpll];
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cpu_parents[1] = clk_output_name[armpll];
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cpu_parents[2] = clk_output_name[ddrpll];
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cpu_parents[3] = clk_output_name[iopll];
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periph_parents[0] = clk_output_name[iopll];
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periph_parents[1] = clk_output_name[iopll];
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periph_parents[2] = clk_output_name[armpll];
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periph_parents[3] = clk_output_name[ddrpll];
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/* ps_clk */
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ret = of_property_read_u32(np, "ps-clk-frequency", &tmp);
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if (ret) {
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pr_warn("ps_clk frequency not specified, using 33 MHz.\n");
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tmp = 33333333;
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}
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ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT,
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tmp);
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/* PLLs */
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clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
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SLCR_PLL_STATUS, 0, &armpll_lock);
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clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
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armpll_parents, 2, 0, SLCR_ARMPLL_CTRL, 4, 1, 0,
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&armpll_lock);
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clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
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SLCR_PLL_STATUS, 1, &ddrpll_lock);
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clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
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ddrpll_parents, 2, 0, SLCR_DDRPLL_CTRL, 4, 1, 0,
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&ddrpll_lock);
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clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
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SLCR_PLL_STATUS, 2, &iopll_lock);
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clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
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iopll_parents, 2, 0, SLCR_IOPLL_CTRL, 4, 1, 0,
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&iopll_lock);
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/* CPU clocks */
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tmp = readl(SLCR_621_TRUE) & 1;
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clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, 0,
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SLCR_ARM_CLK_CTRL, 4, 2, 0, &armclk_lock);
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clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
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SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
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clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],
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"cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
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clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
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1, 2);
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clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
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"cpu_3or2x_div", CLK_IGNORE_UNUSED,
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SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
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clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
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||||
2 + tmp);
|
||||
clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
|
||||
"cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
|
||||
26, 0, &armclk_lock);
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
|
||||
4 + 2 * tmp);
|
||||
clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
|
||||
"cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
|
||||
0, &armclk_lock);
|
||||
|
||||
/* Timers */
|
||||
swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x];
|
||||
for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) {
|
||||
int idx = of_property_match_string(np, "clock-names",
|
||||
swdt_ext_clk_input_names[i]);
|
||||
if (idx >= 0)
|
||||
swdt_ext_clk_mux_parents[i + 1] =
|
||||
of_clk_get_parent_name(np, idx);
|
||||
else
|
||||
swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
|
||||
}
|
||||
clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
|
||||
swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT,
|
||||
SLCR_SWDT_CLK_SEL, 0, 1, 0, &gem0clk_lock);
|
||||
|
||||
/* DDR clocks */
|
||||
clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
|
||||
SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
|
||||
CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
|
||||
clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
|
||||
"ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
|
||||
clk_prepare_enable(clks[ddr2x]);
|
||||
clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
|
||||
SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
|
||||
CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
|
||||
clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
|
||||
"ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
|
||||
clk_prepare_enable(clks[ddr3x]);
|
||||
|
||||
clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
|
||||
SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
|
||||
CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
|
||||
clk = clk_register_divider(NULL, "dci_div1", "dci_div0",
|
||||
CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
|
||||
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
|
||||
&dciclk_lock);
|
||||
clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1",
|
||||
CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0,
|
||||
&dciclk_lock);
|
||||
clk_prepare_enable(clks[dci]);
|
||||
|
||||
/* Peripheral clocks */
|
||||
for (i = fclk0; i <= fclk3; i++)
|
||||
zynq_clk_register_fclk(i, clk_output_name[i],
|
||||
SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
|
||||
periph_parents);
|
||||
|
||||
zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
|
||||
SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
|
||||
|
||||
zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,
|
||||
SLCR_SMC_CLK_CTRL, periph_parents, 0);
|
||||
|
||||
zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,
|
||||
SLCR_PCAP_CLK_CTRL, periph_parents, 0);
|
||||
|
||||
zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
|
||||
clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,
|
||||
periph_parents, 1);
|
||||
|
||||
zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0],
|
||||
clk_output_name[uart1], SLCR_UART_CLK_CTRL,
|
||||
periph_parents, 1);
|
||||
|
||||
zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0],
|
||||
clk_output_name[spi1], SLCR_SPI_CLK_CTRL,
|
||||
periph_parents, 1);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) {
|
||||
int idx = of_property_match_string(np, "clock-names",
|
||||
gem0_emio_input_names[i]);
|
||||
if (idx >= 0)
|
||||
gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
|
||||
idx);
|
||||
}
|
||||
clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4, 0,
|
||||
SLCR_GEM0_CLK_CTRL, 4, 2, 0, &gem0clk_lock);
|
||||
clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
|
||||
SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
|
||||
CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
|
||||
clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",
|
||||
CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
|
||||
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
|
||||
&gem0clk_lock);
|
||||
clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 0,
|
||||
SLCR_GEM0_CLK_CTRL, 6, 1, 0, &gem0clk_lock);
|
||||
clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
|
||||
"gem0_emio_mux", CLK_SET_RATE_PARENT,
|
||||
SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) {
|
||||
int idx = of_property_match_string(np, "clock-names",
|
||||
gem1_emio_input_names[i]);
|
||||
if (idx >= 0)
|
||||
gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
|
||||
idx);
|
||||
}
|
||||
clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4, 0,
|
||||
SLCR_GEM1_CLK_CTRL, 4, 2, 0, &gem1clk_lock);
|
||||
clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
|
||||
SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
|
||||
CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
|
||||
clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",
|
||||
CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
|
||||
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
|
||||
&gem1clk_lock);
|
||||
clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 0,
|
||||
SLCR_GEM1_CLK_CTRL, 6, 1, 0, &gem1clk_lock);
|
||||
clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
|
||||
"gem1_emio_mux", CLK_SET_RATE_PARENT,
|
||||
SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);
|
||||
|
||||
tmp = strlen("mio_clk_00x");
|
||||
clk_name = kmalloc(tmp, GFP_KERNEL);
|
||||
for (i = 0; i < NUM_MIO_PINS; i++) {
|
||||
int idx;
|
||||
|
||||
snprintf(clk_name, tmp, "mio_clk_%2.2d", i);
|
||||
idx = of_property_match_string(np, "clock-names", clk_name);
|
||||
if (idx >= 0)
|
||||
can_mio_mux_parents[i] = of_clk_get_parent_name(np,
|
||||
idx);
|
||||
else
|
||||
can_mio_mux_parents[i] = dummy_nm;
|
||||
}
|
||||
kfree(clk_name);
|
||||
clk = clk_register_mux(NULL, "can_mux", periph_parents, 4, 0,
|
||||
SLCR_CAN_CLK_CTRL, 4, 2, 0, &canclk_lock);
|
||||
clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
|
||||
SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
|
||||
CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
|
||||
clk = clk_register_divider(NULL, "can_div1", "can_div0",
|
||||
CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
|
||||
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
|
||||
&canclk_lock);
|
||||
clk = clk_register_gate(NULL, "can0_gate", "can_div1",
|
||||
CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
|
||||
&canclk_lock);
|
||||
clk = clk_register_gate(NULL, "can1_gate", "can_div1",
|
||||
CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
|
||||
&canclk_lock);
|
||||
clk = clk_register_mux(NULL, "can0_mio_mux",
|
||||
can_mio_mux_parents, 54, CLK_SET_RATE_PARENT,
|
||||
SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, &canmioclk_lock);
|
||||
clk = clk_register_mux(NULL, "can1_mio_mux",
|
||||
can_mio_mux_parents, 54, CLK_SET_RATE_PARENT,
|
||||
SLCR_CAN_MIOCLK_CTRL, 16, 6, 0, &canmioclk_lock);
|
||||
clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
|
||||
can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT,
|
||||
SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, &canmioclk_lock);
|
||||
clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
|
||||
can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT,
|
||||
SLCR_CAN_MIOCLK_CTRL, 22, 1, 0, &canmioclk_lock);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
|
||||
int idx = of_property_match_string(np, "clock-names",
|
||||
dbgtrc_emio_input_names[i]);
|
||||
if (idx >= 0)
|
||||
dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
|
||||
idx);
|
||||
}
|
||||
clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4, 0,
|
||||
SLCR_DBG_CLK_CTRL, 4, 2, 0, &dbgclk_lock);
|
||||
clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
|
||||
SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
|
||||
CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
|
||||
clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, 0,
|
||||
SLCR_DBG_CLK_CTRL, 6, 1, 0, &dbgclk_lock);
|
||||
clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
|
||||
"dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
|
||||
0, 0, &dbgclk_lock);
|
||||
clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb],
|
||||
clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0,
|
||||
&dbgclk_lock);
|
||||
|
||||
/* One gated clock for all APER clocks. */
|
||||
clks[dma] = clk_register_gate(NULL, clk_output_name[dma],
|
||||
clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0,
|
||||
&aperclk_lock);
|
||||
clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper],
|
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0,
|
||||
&aperclk_lock);
|
||||
clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper],
|
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0,
|
||||
&aperclk_lock);
|
||||
clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper],
|
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0,
|
||||
&aperclk_lock);
|
||||
clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper],
|
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0,
|
||||
&aperclk_lock);
|
||||
clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper],
|
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0,
|
||||
&aperclk_lock);
|
||||
clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper],
|
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0,
|
||||
&aperclk_lock);
|
||||
clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper],
|
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0,
|
||||
&aperclk_lock);
|
||||
clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper],
|
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0,
|
||||
&aperclk_lock);
|
||||
clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper],
|
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0,
|
||||
&aperclk_lock);
|
||||
clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper],
|
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0,
|
||||
&aperclk_lock);
|
||||
clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper],
|
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0,
|
||||
&aperclk_lock);
|
||||
clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper],
|
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0,
|
||||
&aperclk_lock);
|
||||
clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper],
|
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0,
|
||||
&aperclk_lock);
|
||||
clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper],
|
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0,
|
||||
&aperclk_lock);
|
||||
clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper],
|
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0,
|
||||
&aperclk_lock);
|
||||
clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper],
|
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0,
|
||||
&aperclk_lock);
|
||||
clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper],
|
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0,
|
||||
&aperclk_lock);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks); i++) {
|
||||
if (IS_ERR(clks[i])) {
|
||||
pr_err("Zynq clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clks[i]));
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
clk_data.clks = clks;
|
||||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
|
||||
|
||||
void __init zynq_clock_init(void __iomem *slcr_base)
|
||||
{
|
||||
zynq_slcr_base_priv = slcr_base;
|
||||
of_clk_init(NULL);
|
||||
}
|
||||
Loading…
Reference in a new issue