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net: dsa: bcm_sf2: Add support for BCM7278 integrated switch
Add support for the integrated switch found on BCM7278:
- core_reg_align is set to 1, to force a translation into the target
address space which is 8 bytes aligned
- an alternate SWITCH_REG layout is provided since registers are largely
bit/masks compatible but have different offsets
- conditional for all CORE_STS_OVERRIDE_{IMP,GMII_P} since those got
moved way out of the traditional register space
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Florian Fainelli
David S. Miller
parent
a78e86ed58
commit
0fe9933804
5 changed files with 68 additions and 10 deletions
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@ -2,7 +2,7 @@
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Required properties:
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- compatible: should be "brcm,bcm7445-switch-v4.0"
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- compatible: should be "brcm,bcm7445-switch-v4.0" or "brcm,bcm7278-switch-v4.0"
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- reg: addresses and length of the register sets for the device, must be 6
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pairs of register addresses and lengths
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- interrupts: interrupts for the devices, must be two interrupts
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@ -1685,6 +1685,18 @@ static const struct b53_chip_data b53_switch_chips[] = {
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.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
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.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
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},
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{
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.chip_id = BCM7278_DEVICE_ID,
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.dev_name = "BCM7278",
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.vlans = 4096,
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.enabled_ports = 0x1ff,
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.arl_entries= 4,
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.cpu_port = B53_CPU_PORT,
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.vta_regs = B53_VTA_REGS,
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.duplex_reg = B53_DUPLEX_STAT_GE,
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.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
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.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
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},
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};
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static int b53_switch_init(struct b53_device *dev)
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@ -62,6 +62,7 @@ enum {
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BCM53019_DEVICE_ID = 0x53019,
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BCM58XX_DEVICE_ID = 0x5800,
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BCM7445_DEVICE_ID = 0x7445,
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BCM7278_DEVICE_ID = 0x7278,
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};
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#define B53_N_PORTS 9
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@ -179,7 +180,8 @@ static inline int is5301x(struct b53_device *dev)
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static inline int is58xx(struct b53_device *dev)
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{
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return dev->chip_id == BCM58XX_DEVICE_ID ||
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dev->chip_id == BCM7445_DEVICE_ID;
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dev->chip_id == BCM7445_DEVICE_ID ||
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dev->chip_id == BCM7278_DEVICE_ID;
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}
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#define B53_CPU_PORT_25 5
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@ -64,7 +64,12 @@ static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
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static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
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{
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struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
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u32 reg, val;
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u32 reg, val, offset;
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if (priv->type == BCM7445_DEVICE_ID)
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offset = CORE_STS_OVERRIDE_IMP;
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else
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offset = CORE_STS_OVERRIDE_IMP2;
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/* Enable the port memories */
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reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
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@ -121,9 +126,9 @@ static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
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core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
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/* Force link status for IMP port */
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reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
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reg = core_readl(priv, offset);
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reg |= (MII_SW_OR | LINK_STS);
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core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
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core_writel(priv, reg, offset);
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}
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static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
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@ -591,7 +596,12 @@ static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
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struct ethtool_eee *p = &priv->port_sts[port].eee;
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u32 id_mode_dis = 0, port_mode;
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const char *str = NULL;
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u32 reg;
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u32 reg, offset;
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if (priv->type == BCM7445_DEVICE_ID)
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offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
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else
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offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
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switch (phydev->interface) {
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case PHY_INTERFACE_MODE_RGMII:
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@ -662,7 +672,7 @@ static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
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if (phydev->duplex == DUPLEX_FULL)
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reg |= DUPLX_MODE;
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core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
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core_writel(priv, reg, offset);
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if (!phydev->is_pseudo_fixed_link)
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p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
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@ -672,9 +682,14 @@ static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
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struct fixed_phy_status *status)
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{
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struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
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u32 duplex, pause;
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u32 duplex, pause, offset;
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u32 reg;
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if (priv->type == BCM7445_DEVICE_ID)
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offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
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else
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offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
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duplex = core_readl(priv, CORE_DUPSTS);
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pause = core_readl(priv, CORE_PAUSESTS);
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@ -703,13 +718,13 @@ static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
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status->duplex = !!(duplex & (1 << port));
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}
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reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(port));
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reg = core_readl(priv, offset);
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reg |= SW_OVERRIDE;
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if (status->link)
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reg |= LINK_STS;
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else
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reg &= ~LINK_STS;
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core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
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core_writel(priv, reg, offset);
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if ((pause & (1 << port)) &&
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(pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
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@ -1038,10 +1053,35 @@ static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
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.reg_offsets = bcm_sf2_7445_reg_offsets,
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};
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static const u16 bcm_sf2_7278_reg_offsets[] = {
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[REG_SWITCH_CNTRL] = 0x00,
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[REG_SWITCH_STATUS] = 0x04,
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[REG_DIR_DATA_WRITE] = 0x08,
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[REG_DIR_DATA_READ] = 0x0c,
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[REG_SWITCH_REVISION] = 0x10,
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[REG_PHY_REVISION] = 0x14,
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[REG_SPHY_CNTRL] = 0x24,
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[REG_RGMII_0_CNTRL] = 0xe0,
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[REG_RGMII_1_CNTRL] = 0xec,
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[REG_RGMII_2_CNTRL] = 0xf8,
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[REG_LED_0_CNTRL] = 0x40,
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[REG_LED_1_CNTRL] = 0x4c,
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[REG_LED_2_CNTRL] = 0x58,
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};
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static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
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.type = BCM7278_DEVICE_ID,
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.core_reg_align = 1,
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.reg_offsets = bcm_sf2_7278_reg_offsets,
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};
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static const struct of_device_id bcm_sf2_of_match[] = {
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{ .compatible = "brcm,bcm7445-switch-v4.0",
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.data = &bcm_sf2_7445_data
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},
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{ .compatible = "brcm,bcm7278-switch-v4.0",
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.data = &bcm_sf2_7278_data
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},
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
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@ -134,6 +134,9 @@ enum bcm_sf2_reg_offs {
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#define GMII_SPEED_UP_2G (1 << 6)
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#define MII_SW_OR (1 << 7)
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/* Alternate layout for e.g: 7278 */
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#define CORE_STS_OVERRIDE_IMP2 0x39040
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#define CORE_NEW_CTRL 0x00084
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#define IP_MC (1 << 0)
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#define OUTRANGEERR_DISCARD (1 << 1)
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@ -151,6 +154,7 @@ enum bcm_sf2_reg_offs {
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#define SW_LEARN_CNTL(x) (1 << (x))
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#define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4)
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#define CORE_STS_OVERRIDE_GMIIP2_PORT(x) (0x39000 + (x) * 8)
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#define LINK_STS (1 << 0)
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#define DUPLX_MODE (1 << 1)
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#define SPEED_SHIFT 2
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