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clk: ast2600: slow down the I3C core clock to 100MHz

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slow down I3C core clock from HCLK200M to APLL800M/8.  This is aimed to
enlarge the max attainable SDA hold time from 35ns (5ns * 7) to 70ns
(10ns * 7).

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I77310414c2f165d2a220d18d8567c07a009d97d7
This commit is contained in:
Dylan Hung 2022-05-11 15:09:37 +08:00
parent 85efe529c4
commit 1a35eb926d
1 changed files with 7 additions and 0 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

7
drivers/clk/clk-ast2600.c
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@ -986,6 +986,13 @@ static void __init aspeed_g6_cc(struct regmap *map)
/* i3c clock */ /* i3c clock */
regmap_read(map, ASPEED_G6_CLK_SELECTION5, &val); regmap_read(map, ASPEED_G6_CLK_SELECTION5, &val);
/* i3c core clock 100MHz (APLL 800MHz / 8) */
val &= ~(I3C_CLK_SELECTION | APLL_DIV_SELECTION);
val |= FIELD_PREP(I3C_CLK_SELECTION, I3C_CLK_SELECT_APLL_DIV);
val |= FIELD_PREP(APLL_DIV_SELECTION, APLL_DIV_8);
regmap_write(map, ASPEED_G6_CLK_SELECTION5, val);
if (FIELD_GET(I3C_CLK_SELECTION, val) == I3C_CLK_SELECT_APLL_DIV) { if (FIELD_GET(I3C_CLK_SELECTION, val) == I3C_CLK_SELECT_APLL_DIV) {
val = FIELD_GET(APLL_DIV_SELECTION, val); val = FIELD_GET(APLL_DIV_SELECTION, val);
if (val) if (val)