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usb: mtu3: support 36-bit DMA address
add support for 36-bit DMA address [ Felipe Balbi: fix printk format for dma_addr_t ] Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
This commit is contained in:
Chunfeng Yun
Felipe Balbi
parent
a316da82f8
commit
1a46dfea08
4 changed files with 142 additions and 21 deletions
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@ -46,6 +46,9 @@ struct mtu3_request;
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#define MU3D_EP_RXCR1(epnum) (U3D_RX1CSR1 + (((epnum) - 1) * 0x10))
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#define MU3D_EP_RXCR2(epnum) (U3D_RX1CSR2 + (((epnum) - 1) * 0x10))
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#define USB_QMU_TQHIAR(epnum) (U3D_TXQHIAR1 + (((epnum) - 1) * 0x4))
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#define USB_QMU_RQHIAR(epnum) (U3D_RXQHIAR1 + (((epnum) - 1) * 0x4))
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#define USB_QMU_RQCSR(epnum) (U3D_RXQCSR1 + (((epnum) - 1) * 0x10))
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#define USB_QMU_RQSAR(epnum) (U3D_RXQSAR1 + (((epnum) - 1) * 0x10))
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#define USB_QMU_RQCPR(epnum) (U3D_RXQCPR1 + (((epnum) - 1) * 0x10))
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@ -138,23 +141,33 @@ struct mtu3_fifo_info {
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* Checksum value is calculated over the 16 bytes of the GPD by default;
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* @data_buf_len (RX ONLY): This value indicates the length of
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* the assigned data buffer
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* @tx_ext_addr (TX ONLY): [3:0] are 4 extension bits of @buffer,
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* [7:4] are 4 extension bits of @next_gpd
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* @next_gpd: Physical address of the next GPD
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* @buffer: Physical address of the data buffer
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* @buf_len:
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* (TX): This value indicates the length of the assigned data buffer
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* (RX): The total length of data received
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* @ext_len: reserved
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* @rx_ext_addr(RX ONLY): [3:0] are 4 extension bits of @buffer,
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* [7:4] are 4 extension bits of @next_gpd
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* @ext_flag:
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* bit5 (TX ONLY): Zero Length Packet (ZLP),
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*/
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struct qmu_gpd {
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__u8 flag;
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__u8 chksum;
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__le16 data_buf_len;
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union {
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__le16 data_buf_len;
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__le16 tx_ext_addr;
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};
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__le32 next_gpd;
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__le32 buffer;
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__le16 buf_len;
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__u8 ext_len;
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union {
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__u8 ext_len;
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__u8 rx_ext_addr;
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};
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__u8 ext_flag;
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} __packed;
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@ -17,6 +17,7 @@
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*
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*/
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#include <linux/dma-mapping.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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@ -759,7 +760,31 @@ static void mtu3_hw_exit(struct mtu3 *mtu)
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mtu3_mem_free(mtu);
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}
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/*-------------------------------------------------------------------------*/
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/**
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* we set 32-bit DMA mask by default, here check whether the controller
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* supports 36-bit DMA or not, if it does, set 36-bit DMA mask.
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*/
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static int mtu3_set_dma_mask(struct mtu3 *mtu)
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{
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struct device *dev = mtu->dev;
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bool is_36bit = false;
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int ret = 0;
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u32 value;
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value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL);
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if (value & DMA_ADDR_36BIT) {
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is_36bit = true;
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
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/* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */
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if (ret) {
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is_36bit = false;
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
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}
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}
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dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32");
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return ret;
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}
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int ssusb_gadget_init(struct ssusb_mtk *ssusb)
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{
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@ -820,6 +845,12 @@ int ssusb_gadget_init(struct ssusb_mtk *ssusb)
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return ret;
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}
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ret = mtu3_set_dma_mask(mtu);
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if (ret) {
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dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret);
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goto dma_mask_err;
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}
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ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu);
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if (ret) {
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dev_err(dev, "request irq %d failed!\n", mtu->irq);
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@ -845,6 +876,7 @@ int ssusb_gadget_init(struct ssusb_mtk *ssusb)
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gadget_err:
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device_init_wakeup(dev, false);
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dma_mask_err:
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irq_err:
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mtu3_hw_exit(mtu);
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ssusb->u3d = NULL;
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@ -58,6 +58,8 @@
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#define U3D_QCR1 (SSUSB_DEV_BASE + 0x0404)
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#define U3D_QCR2 (SSUSB_DEV_BASE + 0x0408)
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#define U3D_QCR3 (SSUSB_DEV_BASE + 0x040C)
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#define U3D_TXQHIAR1 (SSUSB_DEV_BASE + 0x0484)
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#define U3D_RXQHIAR1 (SSUSB_DEV_BASE + 0x04C4)
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#define U3D_TXQCSR1 (SSUSB_DEV_BASE + 0x0510)
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#define U3D_TXQSAR1 (SSUSB_DEV_BASE + 0x0514)
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@ -189,6 +191,13 @@
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#define QMU_RX_COZ(x) (BIT(16) << (x))
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#define QMU_RX_ZLP(x) (BIT(0) << (x))
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/* U3D_TXQHIAR1 */
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/* U3D_RXQHIAR1 */
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#define QMU_LAST_DONE_PTR_HI(x) (((x) >> 16) & 0xf)
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#define QMU_CUR_GPD_ADDR_HI(x) (((x) >> 8) & 0xf)
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#define QMU_START_ADDR_HI_MSK GENMASK(3, 0)
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#define QMU_START_ADDR_HI(x) (((x) & 0xf) << 0)
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/* U3D_TXQCSR1 */
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/* U3D_RXQCSR1 */
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#define QMU_Q_ACTIVE BIT(15)
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@ -225,6 +234,7 @@
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#define CAP_TX_EP_NUM(x) ((x) & 0x1f)
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/* U3D_MISC_CTRL */
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#define DMA_ADDR_36BIT BIT(31)
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#define VBUS_ON BIT(1)
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#define VBUS_FRC_EN BIT(0)
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@ -40,7 +40,58 @@
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#define GPD_FLAGS_IOC BIT(7)
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#define GPD_EXT_FLAG_ZLP BIT(5)
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#define GPD_EXT_NGP(x) (((x) & 0xf) << 4)
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#define GPD_EXT_BUF(x) (((x) & 0xf) << 0)
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#define HILO_GEN64(hi, lo) (((u64)(hi) << 32) + (lo))
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#define HILO_DMA(hi, lo) \
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((dma_addr_t)HILO_GEN64((le32_to_cpu(hi)), (le32_to_cpu(lo))))
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static dma_addr_t read_txq_cur_addr(void __iomem *mbase, u8 epnum)
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{
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u32 txcpr;
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u32 txhiar;
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txcpr = mtu3_readl(mbase, USB_QMU_TQCPR(epnum));
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txhiar = mtu3_readl(mbase, USB_QMU_TQHIAR(epnum));
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return HILO_DMA(QMU_CUR_GPD_ADDR_HI(txhiar), txcpr);
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}
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static dma_addr_t read_rxq_cur_addr(void __iomem *mbase, u8 epnum)
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{
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u32 rxcpr;
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u32 rxhiar;
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rxcpr = mtu3_readl(mbase, USB_QMU_RQCPR(epnum));
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rxhiar = mtu3_readl(mbase, USB_QMU_RQHIAR(epnum));
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return HILO_DMA(QMU_CUR_GPD_ADDR_HI(rxhiar), rxcpr);
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}
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static void write_txq_start_addr(void __iomem *mbase, u8 epnum, dma_addr_t dma)
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{
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u32 tqhiar;
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mtu3_writel(mbase, USB_QMU_TQSAR(epnum),
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cpu_to_le32(lower_32_bits(dma)));
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tqhiar = mtu3_readl(mbase, USB_QMU_TQHIAR(epnum));
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tqhiar &= ~QMU_START_ADDR_HI_MSK;
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tqhiar |= QMU_START_ADDR_HI(upper_32_bits(dma));
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mtu3_writel(mbase, USB_QMU_TQHIAR(epnum), tqhiar);
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}
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static void write_rxq_start_addr(void __iomem *mbase, u8 epnum, dma_addr_t dma)
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{
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u32 rqhiar;
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mtu3_writel(mbase, USB_QMU_RQSAR(epnum),
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cpu_to_le32(lower_32_bits(dma)));
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rqhiar = mtu3_readl(mbase, USB_QMU_RQHIAR(epnum));
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rqhiar &= ~QMU_START_ADDR_HI_MSK;
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rqhiar |= QMU_START_ADDR_HI(upper_32_bits(dma));
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mtu3_writel(mbase, USB_QMU_RQHIAR(epnum), rqhiar);
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}
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static struct qmu_gpd *gpd_dma_to_virt(struct mtu3_gpd_ring *ring,
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dma_addr_t dma_addr)
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@ -193,21 +244,27 @@ static int mtu3_prepare_tx_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq)
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struct mtu3_gpd_ring *ring = &mep->gpd_ring;
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struct qmu_gpd *gpd = ring->enqueue;
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struct usb_request *req = &mreq->request;
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dma_addr_t enq_dma;
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u16 ext_addr;
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/* set all fields to zero as default value */
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memset(gpd, 0, sizeof(*gpd));
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gpd->buffer = cpu_to_le32((u32)req->dma);
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gpd->buffer = cpu_to_le32(lower_32_bits(req->dma));
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ext_addr = GPD_EXT_BUF(upper_32_bits(req->dma));
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gpd->buf_len = cpu_to_le16(req->length);
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gpd->flag |= GPD_FLAGS_IOC;
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/* get the next GPD */
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enq = advance_enq_gpd(ring);
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dev_dbg(mep->mtu->dev, "TX-EP%d queue gpd=%p, enq=%p\n",
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mep->epnum, gpd, enq);
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enq_dma = gpd_virt_to_dma(ring, enq);
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dev_dbg(mep->mtu->dev, "TX-EP%d queue gpd=%p, enq=%p, qdma=%pad\n",
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mep->epnum, gpd, enq, enq_dma);
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enq->flag &= ~GPD_FLAGS_HWO;
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gpd->next_gpd = cpu_to_le32((u32)gpd_virt_to_dma(ring, enq));
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gpd->next_gpd = cpu_to_le32(lower_32_bits(enq_dma));
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ext_addr |= GPD_EXT_NGP(upper_32_bits(enq_dma));
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gpd->tx_ext_addr = cpu_to_le16(ext_addr);
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if (req->zero)
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gpd->ext_flag |= GPD_EXT_FLAG_ZLP;
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@ -226,21 +283,27 @@ static int mtu3_prepare_rx_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq)
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struct mtu3_gpd_ring *ring = &mep->gpd_ring;
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struct qmu_gpd *gpd = ring->enqueue;
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struct usb_request *req = &mreq->request;
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dma_addr_t enq_dma;
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u16 ext_addr;
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/* set all fields to zero as default value */
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memset(gpd, 0, sizeof(*gpd));
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gpd->buffer = cpu_to_le32((u32)req->dma);
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gpd->buffer = cpu_to_le32(lower_32_bits(req->dma));
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ext_addr = GPD_EXT_BUF(upper_32_bits(req->dma));
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gpd->data_buf_len = cpu_to_le16(req->length);
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gpd->flag |= GPD_FLAGS_IOC;
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/* get the next GPD */
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enq = advance_enq_gpd(ring);
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dev_dbg(mep->mtu->dev, "RX-EP%d queue gpd=%p, enq=%p\n",
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mep->epnum, gpd, enq);
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enq_dma = gpd_virt_to_dma(ring, enq);
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dev_dbg(mep->mtu->dev, "RX-EP%d queue gpd=%p, enq=%p, qdma=%pad\n",
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mep->epnum, gpd, enq, enq_dma);
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enq->flag &= ~GPD_FLAGS_HWO;
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gpd->next_gpd = cpu_to_le32((u32)gpd_virt_to_dma(ring, enq));
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gpd->next_gpd = cpu_to_le32(lower_32_bits(enq_dma));
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ext_addr |= GPD_EXT_NGP(upper_32_bits(enq_dma));
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gpd->rx_ext_addr = cpu_to_le16(ext_addr);
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gpd->chksum = qmu_calc_checksum((u8 *)gpd);
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gpd->flag |= GPD_FLAGS_HWO;
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@ -267,8 +330,8 @@ int mtu3_qmu_start(struct mtu3_ep *mep)
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if (mep->is_in) {
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/* set QMU start address */
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mtu3_writel(mbase, USB_QMU_TQSAR(mep->epnum), ring->dma);
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mtu3_setbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_DMAREQEN);
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write_txq_start_addr(mbase, epnum, ring->dma);
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mtu3_setbits(mbase, MU3D_EP_TXCR0(epnum), TX_DMAREQEN);
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mtu3_setbits(mbase, U3D_QCR0, QMU_TX_CS_EN(epnum));
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/* send zero length packet according to ZLP flag in GPD */
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mtu3_setbits(mbase, U3D_QCR1, QMU_TX_ZLP(epnum));
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@ -282,8 +345,8 @@ int mtu3_qmu_start(struct mtu3_ep *mep)
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mtu3_writel(mbase, USB_QMU_TQCSR(epnum), QMU_Q_START);
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} else {
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mtu3_writel(mbase, USB_QMU_RQSAR(mep->epnum), ring->dma);
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mtu3_setbits(mbase, MU3D_EP_RXCR0(mep->epnum), RX_DMAREQEN);
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write_rxq_start_addr(mbase, epnum, ring->dma);
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mtu3_setbits(mbase, MU3D_EP_RXCR0(epnum), RX_DMAREQEN);
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mtu3_setbits(mbase, U3D_QCR0, QMU_RX_CS_EN(epnum));
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/* don't expect ZLP */
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mtu3_clrbits(mbase, U3D_QCR3, QMU_RX_ZLP(epnum));
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@ -353,9 +416,9 @@ static void qmu_tx_zlp_error_handler(struct mtu3 *mtu, u8 epnum)
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struct mtu3_gpd_ring *ring = &mep->gpd_ring;
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void __iomem *mbase = mtu->mac_base;
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struct qmu_gpd *gpd_current = NULL;
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dma_addr_t gpd_dma = mtu3_readl(mbase, USB_QMU_TQCPR(epnum));
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struct usb_request *req = NULL;
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struct mtu3_request *mreq;
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dma_addr_t cur_gpd_dma;
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u32 txcsr = 0;
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int ret;
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@ -365,7 +428,8 @@ static void qmu_tx_zlp_error_handler(struct mtu3 *mtu, u8 epnum)
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else
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return;
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gpd_current = gpd_dma_to_virt(ring, gpd_dma);
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cur_gpd_dma = read_txq_cur_addr(mbase, epnum);
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gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma);
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if (le16_to_cpu(gpd_current->buf_len) != 0) {
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dev_err(mtu->dev, "TX EP%d buffer length error(!=0)\n", epnum);
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@ -408,12 +472,13 @@ static void qmu_done_tx(struct mtu3 *mtu, u8 epnum)
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void __iomem *mbase = mtu->mac_base;
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struct qmu_gpd *gpd = ring->dequeue;
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struct qmu_gpd *gpd_current = NULL;
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dma_addr_t gpd_dma = mtu3_readl(mbase, USB_QMU_TQCPR(epnum));
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struct usb_request *request = NULL;
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struct mtu3_request *mreq;
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dma_addr_t cur_gpd_dma;
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/*transfer phy address got from QMU register to virtual address */
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gpd_current = gpd_dma_to_virt(ring, gpd_dma);
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cur_gpd_dma = read_txq_cur_addr(mbase, epnum);
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gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma);
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dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n",
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__func__, epnum, gpd, gpd_current, ring->enqueue);
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@ -446,11 +511,12 @@ static void qmu_done_rx(struct mtu3 *mtu, u8 epnum)
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void __iomem *mbase = mtu->mac_base;
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struct qmu_gpd *gpd = ring->dequeue;
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struct qmu_gpd *gpd_current = NULL;
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dma_addr_t gpd_dma = mtu3_readl(mbase, USB_QMU_RQCPR(epnum));
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struct usb_request *req = NULL;
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struct mtu3_request *mreq;
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dma_addr_t cur_gpd_dma;
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gpd_current = gpd_dma_to_virt(ring, gpd_dma);
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cur_gpd_dma = read_rxq_cur_addr(mbase, epnum);
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gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma);
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dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n",
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__func__, epnum, gpd, gpd_current, ring->enqueue);
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