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sb_edac: Add support for Broadwell-DE processor
Broadwell-DE is the microserver version of next generation Xeon processors. A whole bunch of new PCIe device ids, but otherwise pretty much the same as Haswell. Acked-by: Aristeu Rozanski <aris@redhat.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
This commit is contained in:
Tony Luck
Mauro Carvalho Chehab
parent
f7cf2a22a2
commit
1f39581a9a
1 changed files with 157 additions and 6 deletions
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@ -262,6 +262,7 @@ enum type {
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SANDY_BRIDGE,
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IVY_BRIDGE,
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HASWELL,
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BROADWELL,
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};
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struct sbridge_pvt;
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@ -446,7 +447,7 @@ static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
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* - each SMI channel interfaces with a scalable memory buffer
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* - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
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*/
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#define HASWELL_DDRCRCLKCONTROLS 0xa10
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#define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */
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#define HASWELL_HASYSDEFEATURE2 0x84
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0
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@ -497,6 +498,46 @@ static const struct pci_id_table pci_dev_descr_haswell_table[] = {
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{0,} /* 0 terminated list. */
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};
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/*
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* Broadwell support
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*
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* DE processor:
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* - 1 IMC
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* - 2 DDR3 channels, 2 DPC per channel
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*/
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL 0x6f71
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad
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#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf
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static const struct pci_id_descr pci_dev_descr_broadwell[] = {
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/* first item must be the HA */
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1) },
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};
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static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
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PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell),
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{0,} /* 0 terminated list. */
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};
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/*
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* pci_device_id table for which devices we are looking for
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*/
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@ -504,6 +545,7 @@ static const struct pci_device_id sbridge_pci_tbl[] = {
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0)},
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{0,} /* 0 terminated list. */
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};
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@ -768,12 +810,22 @@ static int check_if_ecc_is_active(const u8 bus, enum type type)
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struct pci_dev *pdev = NULL;
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u32 mcmtr, id;
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if (type == IVY_BRIDGE)
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switch (type) {
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case IVY_BRIDGE:
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id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA;
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else if (type == HASWELL)
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break;
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case HASWELL:
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id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA;
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else
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break;
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case SANDY_BRIDGE:
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id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA;
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break;
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case BROADWELL:
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id = PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA;
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break;
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default:
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return -ENODEV;
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}
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pdev = get_pdev_same_bus(bus, id);
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if (!pdev) {
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@ -801,7 +853,7 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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enum edac_type mode;
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enum mem_type mtype;
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if (pvt->info.type == HASWELL)
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if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL)
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pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®);
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else
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pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®);
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@ -1182,7 +1234,7 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
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*socket = sad_interleave[idx];
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edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
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idx, sad_way, *socket);
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} else if (pvt->info.type == HASWELL) {
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} else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
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int bits, a7mode = A7MODE(dram_rule);
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if (a7mode) {
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@ -1831,6 +1883,82 @@ static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
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return -ENODEV;
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}
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static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
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struct sbridge_dev *sbridge_dev)
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{
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struct sbridge_pvt *pvt = mci->pvt_info;
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struct pci_dev *pdev;
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int i;
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/* there's only one device per system; not tied to any bus */
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if (pvt->info.pci_vtd == NULL)
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/* result will be checked later */
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pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC,
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NULL);
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for (i = 0; i < sbridge_dev->n_devs; i++) {
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pdev = sbridge_dev->pdev[i];
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if (!pdev)
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continue;
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switch (pdev->device) {
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case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:
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pvt->pci_sad0 = pdev;
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break;
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case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:
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pvt->pci_sad1 = pdev;
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break;
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case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
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pvt->pci_ha0 = pdev;
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break;
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case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
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pvt->pci_ta = pdev;
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break;
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case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL:
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pvt->pci_ras = pdev;
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break;
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case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
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pvt->pci_tad[0] = pdev;
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break;
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case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:
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pvt->pci_tad[1] = pdev;
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break;
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case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:
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pvt->pci_tad[2] = pdev;
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break;
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case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:
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pvt->pci_tad[3] = pdev;
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break;
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case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:
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pvt->pci_ddrio = pdev;
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break;
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default:
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break;
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}
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edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
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sbridge_dev->bus,
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PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
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pdev);
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}
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/* Check if everything were registered */
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if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
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!pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
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goto enodev;
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for (i = 0; i < NUM_CHANNELS; i++) {
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if (!pvt->pci_tad[i])
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goto enodev;
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}
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return 0;
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enodev:
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sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
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return -ENODEV;
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}
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/****************************************************************************
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Error check routines
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****************************************************************************/
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@ -2243,6 +2371,25 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
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if (unlikely(rc < 0))
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goto fail0;
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break;
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case BROADWELL:
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/* rankcfgr isn't used */
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pvt->info.get_tolm = haswell_get_tolm;
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pvt->info.get_tohm = haswell_get_tohm;
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pvt->info.dram_rule = ibridge_dram_rule;
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pvt->info.get_memory_type = haswell_get_memory_type;
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pvt->info.get_node_id = haswell_get_node_id;
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pvt->info.rir_limit = haswell_rir_limit;
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pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
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pvt->info.interleave_list = ibridge_interleave_list;
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pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
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pvt->info.interleave_pkg = ibridge_interleave_pkg;
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mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell Socket#%d", mci->mc_idx);
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/* Store pci devices at mci for faster access */
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rc = broadwell_mci_bind_devs(mci, sbridge_dev);
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if (unlikely(rc < 0))
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goto fail0;
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break;
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}
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/* Get dimm basic config and the memory layout */
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@ -2308,6 +2455,10 @@ static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_haswell_table);
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type = HASWELL;
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break;
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case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
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rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_broadwell_table);
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type = BROADWELL;
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break;
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}
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if (unlikely(rc < 0))
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goto fail0;
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