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MIPS: smp-cps: rework core/VPE initialisation
When hotplug and/or a powered down idle state are supported cases will
arise where a non-zero VPE must be brought online without VPE 0, and it
where multiple VPEs must be onlined simultaneously. This patch prepares
for that by:
- Splitting struct boot_config into core & VPE boot config structures,
allocated one per core or VPE respectively. This allows for multiple
VPEs to be onlined simultaneously without clobbering each others
configuration.
- Indicating which VPEs should be online within a core at any given
time using a bitmap. This allows multiple VPEs to be brought online
simultaneously and also indicates to VPE 0 whether it should halt
after starting any non-zero VPEs that should be online within the
core. For example if all VPEs within a core are offlined via hotplug
and the user onlines the second VPE within that core:
1) The core will be powered up.
2) VPE 0 will run from the BEV (ie. mips_cps_core_entry) to
initialise the core.
3) VPE 0 will start VPE 1 because its bit is set in the cores
bitmap.
4) VPE 0 will halt itself because its bit is clear in the cores
bitmap.
- Moving the core & VPE initialisation to assembly code which does not
make any use of the stack. This is because if a non-zero VPE is to
be brought online in a powered down core then when VPE 0 of that
core runs it may not have a valid stack, and even if it did then
it's messy to run through parts of generic kernel code on VPE 0
before starting the correct VPE.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
This commit is contained in:
Paul Burton
parent
d674dd14e8
commit
245a7868d2
5 changed files with 374 additions and 161 deletions
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@ -13,17 +13,23 @@
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#ifndef __ASSEMBLY__
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struct boot_config {
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unsigned int core;
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unsigned int vpe;
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struct vpe_boot_config {
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unsigned long pc;
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unsigned long sp;
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unsigned long gp;
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};
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extern struct boot_config mips_cps_bootcfg;
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struct core_boot_config {
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atomic_t vpe_mask;
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struct vpe_boot_config *vpe_config;
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};
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extern struct core_boot_config *mips_cps_core_bootcfg;
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extern void mips_cps_core_entry(void);
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extern void mips_cps_core_init(void);
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extern struct vpe_boot_config *mips_cps_boot_vpes(void);
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#else /* __ASSEMBLY__ */
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@ -487,10 +487,14 @@ void output_kvm_defines(void)
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void output_cps_defines(void)
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{
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COMMENT(" MIPS CPS offsets. ");
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OFFSET(BOOTCFG_CORE, boot_config, core);
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OFFSET(BOOTCFG_VPE, boot_config, vpe);
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OFFSET(BOOTCFG_PC, boot_config, pc);
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OFFSET(BOOTCFG_SP, boot_config, sp);
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OFFSET(BOOTCFG_GP, boot_config, gp);
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OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask);
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OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config);
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DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config));
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OFFSET(VPEBOOTCFG_PC, vpe_boot_config, pc);
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OFFSET(VPEBOOTCFG_SP, vpe_boot_config, sp);
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OFFSET(VPEBOOTCFG_GP, vpe_boot_config, gp);
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DEFINE(VPEBOOTCFG_SIZE, sizeof(struct vpe_boot_config));
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}
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#endif
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@ -14,12 +14,33 @@
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#include <asm/asmmacro.h>
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#include <asm/cacheops.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#define GCR_CL_COHERENCE_OFS 0x2008
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#define GCR_CL_COHERENCE_OFS 0x2008
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#define GCR_CL_ID_OFS 0x2028
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.extern mips_cm_base
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.set noreorder
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/*
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* Set dest to non-zero if the core supports the MT ASE, else zero. If
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* MT is not supported then branch to nomt.
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*/
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.macro has_mt dest, nomt
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mfc0 \dest, CP0_CONFIG
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bgez \dest, \nomt
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mfc0 \dest, CP0_CONFIG, 1
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bgez \dest, \nomt
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mfc0 \dest, CP0_CONFIG, 2
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bgez \dest, \nomt
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mfc0 \dest, CP0_CONFIG, 3
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andi \dest, \dest, MIPS_CONF3_MT
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beqz \dest, \nomt
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.endm
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.section .text.cps-vec
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.balign 0x1000
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.set noreorder
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LEAF(mips_cps_core_entry)
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/*
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@ -134,21 +155,24 @@ dcache_done:
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jr t0
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nop
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1: /* We're up, cached & coherent */
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/*
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* We're up, cached & coherent. Perform any further required core-level
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* initialisation.
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*/
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1: jal mips_cps_core_init
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nop
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/*
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* TODO: We should check the VPE number we intended to boot here, and
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* if non-zero we should start that VPE and stop this one. For
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* the moment this doesn't matter since CPUs are brought up
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* sequentially and in order, but once hotplug is implemented
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* this will need revisiting.
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* Boot any other VPEs within this core that should be online, and
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* deactivate this VPE if it should be offline.
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*/
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jal mips_cps_boot_vpes
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nop
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/* Off we go! */
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la t0, mips_cps_bootcfg
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lw t1, BOOTCFG_PC(t0)
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lw gp, BOOTCFG_GP(t0)
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lw sp, BOOTCFG_SP(t0)
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lw t1, VPEBOOTCFG_PC(v0)
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lw gp, VPEBOOTCFG_GP(v0)
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lw sp, VPEBOOTCFG_SP(v0)
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jr t1
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nop
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END(mips_cps_core_entry)
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@ -189,3 +213,237 @@ LEAF(excep_ejtag)
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jr k0
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nop
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END(excep_ejtag)
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LEAF(mips_cps_core_init)
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#ifdef CONFIG_MIPS_MT
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/* Check that the core implements the MT ASE */
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has_mt t0, 3f
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nop
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.set push
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.set mt
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/* Only allow 1 TC per VPE to execute... */
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dmt
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/* ...and for the moment only 1 VPE */
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dvpe
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la t1, 1f
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jr.hb t1
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nop
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/* Enter VPE configuration state */
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1: mfc0 t0, CP0_MVPCONTROL
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ori t0, t0, MVPCONTROL_VPC
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mtc0 t0, CP0_MVPCONTROL
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/* Retrieve the number of VPEs within the core */
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mfc0 t0, CP0_MVPCONF0
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srl t0, t0, MVPCONF0_PVPE_SHIFT
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andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
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addi t7, t0, 1
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/* If there's only 1, we're done */
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beqz t0, 2f
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nop
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/* Loop through each VPE within this core */
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li t5, 1
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1: /* Operate on the appropriate TC */
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mtc0 t5, CP0_VPECONTROL
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ehb
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/* Bind TC to VPE (1:1 TC:VPE mapping) */
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mttc0 t5, CP0_TCBIND
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/* Set exclusive TC, non-active, master */
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li t0, VPECONF0_MVP
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sll t1, t5, VPECONF0_XTC_SHIFT
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or t0, t0, t1
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mttc0 t0, CP0_VPECONF0
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/* Set TC non-active, non-allocatable */
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mttc0 zero, CP0_TCSTATUS
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/* Set TC halted */
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li t0, TCHALT_H
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mttc0 t0, CP0_TCHALT
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/* Next VPE */
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addi t5, t5, 1
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slt t0, t5, t7
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bnez t0, 1b
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nop
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/* Leave VPE configuration state */
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2: mfc0 t0, CP0_MVPCONTROL
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xori t0, t0, MVPCONTROL_VPC
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mtc0 t0, CP0_MVPCONTROL
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3: .set pop
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#endif
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jr ra
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nop
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END(mips_cps_core_init)
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LEAF(mips_cps_boot_vpes)
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/* Retrieve CM base address */
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la t0, mips_cm_base
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lw t0, 0(t0)
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/* Calculate a pointer to this cores struct core_boot_config */
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lw t0, GCR_CL_ID_OFS(t0)
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li t1, COREBOOTCFG_SIZE
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mul t0, t0, t1
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la t1, mips_cps_core_bootcfg
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lw t1, 0(t1)
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addu t0, t0, t1
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/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
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has_mt t6, 1f
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li t9, 0
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/* Find the number of VPEs present in the core */
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mfc0 t1, CP0_MVPCONF0
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srl t1, t1, MVPCONF0_PVPE_SHIFT
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andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
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addi t1, t1, 1
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/* Calculate a mask for the VPE ID from EBase.CPUNum */
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clz t1, t1
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li t2, 31
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subu t1, t2, t1
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li t2, 1
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sll t1, t2, t1
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addiu t1, t1, -1
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/* Retrieve the VPE ID from EBase.CPUNum */
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mfc0 t9, $15, 1
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and t9, t9, t1
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1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
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li t1, VPEBOOTCFG_SIZE
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mul v0, t9, t1
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lw t7, COREBOOTCFG_VPECONFIG(t0)
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addu v0, v0, t7
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#ifdef CONFIG_MIPS_MT
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/* If the core doesn't support MT then return */
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bnez t6, 1f
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nop
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jr ra
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nop
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.set push
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.set mt
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1: /* Enter VPE configuration state */
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dvpe
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la t1, 1f
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jr.hb t1
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nop
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1: mfc0 t1, CP0_MVPCONTROL
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ori t1, t1, MVPCONTROL_VPC
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mtc0 t1, CP0_MVPCONTROL
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ehb
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/* Loop through each VPE */
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lw t6, COREBOOTCFG_VPEMASK(t0)
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move t8, t6
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li t5, 0
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/* Check whether the VPE should be running. If not, skip it */
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1: andi t0, t6, 1
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beqz t0, 2f
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nop
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/* Operate on the appropriate TC */
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mfc0 t0, CP0_VPECONTROL
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ori t0, t0, VPECONTROL_TARGTC
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xori t0, t0, VPECONTROL_TARGTC
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or t0, t0, t5
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mtc0 t0, CP0_VPECONTROL
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ehb
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/* Skip the VPE if its TC is not halted */
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mftc0 t0, CP0_TCHALT
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beqz t0, 2f
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nop
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/* Calculate a pointer to the VPEs struct vpe_boot_config */
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li t0, VPEBOOTCFG_SIZE
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mul t0, t0, t5
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addu t0, t0, t7
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/* Set the TC restart PC */
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lw t1, VPEBOOTCFG_PC(t0)
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mttc0 t1, CP0_TCRESTART
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/* Set the TC stack pointer */
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lw t1, VPEBOOTCFG_SP(t0)
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mttgpr t1, sp
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/* Set the TC global pointer */
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lw t1, VPEBOOTCFG_GP(t0)
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mttgpr t1, gp
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/* Copy config from this VPE */
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mfc0 t0, CP0_CONFIG
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mttc0 t0, CP0_CONFIG
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/* Ensure no software interrupts are pending */
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mttc0 zero, CP0_CAUSE
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mttc0 zero, CP0_STATUS
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/* Set TC active, not interrupt exempt */
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mftc0 t0, CP0_TCSTATUS
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li t1, ~TCSTATUS_IXMT
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and t0, t0, t1
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ori t0, t0, TCSTATUS_A
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mttc0 t0, CP0_TCSTATUS
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/* Clear the TC halt bit */
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mttc0 zero, CP0_TCHALT
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/* Set VPE active */
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mftc0 t0, CP0_VPECONF0
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ori t0, t0, VPECONF0_VPA
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mttc0 t0, CP0_VPECONF0
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/* Next VPE */
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2: srl t6, t6, 1
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addi t5, t5, 1
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bnez t6, 1b
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nop
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/* Leave VPE configuration state */
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mfc0 t1, CP0_MVPCONTROL
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xori t1, t1, MVPCONTROL_VPC
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mtc0 t1, CP0_MVPCONTROL
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ehb
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evpe
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/* Check whether this VPE is meant to be running */
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li t0, 1
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sll t0, t0, t9
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and t0, t0, t8
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bnez t0, 2f
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nop
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/* This VPE should be offline, halt the TC */
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li t0, TCHALT_H
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mtc0 t0, CP0_TCHALT
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la t0, 1f
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1: jr.hb t0
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nop
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2: .set pop
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#endif /* CONFIG_MIPS_MT */
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/* Return */
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jr ra
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nop
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END(mips_cps_boot_vpes)
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@ -9,6 +9,8 @@
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*/
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#include <linux/errno.h>
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#include <linux/percpu.h>
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#include <linux/spinlock.h>
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#include <asm/mips-cm.h>
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#include <asm/mips-cpc.h>
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@ -26,98 +26,37 @@
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static DECLARE_BITMAP(core_power, NR_CPUS);
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struct boot_config mips_cps_bootcfg;
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struct core_boot_config *mips_cps_core_bootcfg;
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static void init_core(void)
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static unsigned core_vpe_count(unsigned core)
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{
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unsigned int nvpes, t;
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u32 mvpconf0, vpeconf0, vpecontrol, tcstatus, tcbind, status;
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unsigned cfg;
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if (!cpu_has_mipsmt)
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return;
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if (!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
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return 1;
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/* Enter VPE configuration state */
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dvpe();
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set_c0_mvpcontrol(MVPCONTROL_VPC);
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/* Retrieve the count of VPEs in this core */
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mvpconf0 = read_c0_mvpconf0();
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nvpes = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
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smp_num_siblings = nvpes;
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for (t = 1; t < nvpes; t++) {
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/* Use a 1:1 mapping of TC index to VPE index */
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settc(t);
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/* Bind 1 TC to this VPE */
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tcbind = read_tc_c0_tcbind();
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tcbind &= ~TCBIND_CURVPE;
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tcbind |= t << TCBIND_CURVPE_SHIFT;
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write_tc_c0_tcbind(tcbind);
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/* Set exclusive TC, non-active, master */
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vpeconf0 = read_vpe_c0_vpeconf0();
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vpeconf0 &= ~(VPECONF0_XTC | VPECONF0_VPA);
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vpeconf0 |= t << VPECONF0_XTC_SHIFT;
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vpeconf0 |= VPECONF0_MVP;
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write_vpe_c0_vpeconf0(vpeconf0);
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/* Declare TC non-active, non-allocatable & interrupt exempt */
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tcstatus = read_tc_c0_tcstatus();
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tcstatus &= ~(TCSTATUS_A | TCSTATUS_DA);
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tcstatus |= TCSTATUS_IXMT;
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write_tc_c0_tcstatus(tcstatus);
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/* Halt the TC */
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write_tc_c0_tchalt(TCHALT_H);
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/* Allow only 1 TC to execute */
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vpecontrol = read_vpe_c0_vpecontrol();
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vpecontrol &= ~VPECONTROL_TE;
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write_vpe_c0_vpecontrol(vpecontrol);
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/* Copy (most of) Status from VPE 0 */
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status = read_c0_status();
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status &= ~(ST0_IM | ST0_IE | ST0_KSU);
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status |= ST0_CU0;
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write_vpe_c0_status(status);
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/* Copy Config from VPE 0 */
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write_vpe_c0_config(read_c0_config());
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write_vpe_c0_config7(read_c0_config7());
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/* Ensure no software interrupts are pending */
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write_vpe_c0_cause(0);
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/* Sync Count */
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write_vpe_c0_count(read_c0_count());
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}
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/* Leave VPE configuration state */
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clear_c0_mvpcontrol(MVPCONTROL_VPC);
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write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
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cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
|
||||
return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
|
||||
}
|
||||
|
||||
static void __init cps_smp_setup(void)
|
||||
{
|
||||
unsigned int ncores, nvpes, core_vpes;
|
||||
int c, v;
|
||||
u32 core_cfg, *entry_code;
|
||||
u32 *entry_code;
|
||||
|
||||
/* Detect & record VPE topology */
|
||||
ncores = mips_cm_numcores();
|
||||
pr_info("VPE topology ");
|
||||
for (c = nvpes = 0; c < ncores; c++) {
|
||||
if (cpu_has_mipsmt && config_enabled(CONFIG_MIPS_MT_SMP)) {
|
||||
write_gcr_cl_other(c << CM_GCR_Cx_OTHER_CORENUM_SHF);
|
||||
core_cfg = read_gcr_co_config();
|
||||
core_vpes = ((core_cfg & CM_GCR_Cx_CONFIG_PVPE_MSK) >>
|
||||
CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
|
||||
} else {
|
||||
core_vpes = 1;
|
||||
}
|
||||
|
||||
core_vpes = core_vpe_count(c);
|
||||
pr_cont("%c%u", c ? ',' : '{', core_vpes);
|
||||
|
||||
/* Use the number of VPEs in core 0 for smp_num_siblings */
|
||||
if (!c)
|
||||
smp_num_siblings = core_vpes;
|
||||
|
||||
for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
|
||||
cpu_data[nvpes + v].core = c;
|
||||
#ifdef CONFIG_MIPS_MT_SMP
|
||||
|
|
@ -140,12 +79,8 @@ static void __init cps_smp_setup(void)
|
|||
/* Core 0 is powered up (we're running on it) */
|
||||
bitmap_set(core_power, 0, 1);
|
||||
|
||||
/* Disable MT - we only want to run 1 TC per VPE */
|
||||
if (cpu_has_mipsmt)
|
||||
dmt();
|
||||
|
||||
/* Initialise core 0 */
|
||||
init_core();
|
||||
mips_cps_core_init();
|
||||
|
||||
/* Patch the start of mips_cps_core_entry to provide the CM base */
|
||||
entry_code = (u32 *)&mips_cps_core_entry;
|
||||
|
|
@ -157,15 +92,60 @@ static void __init cps_smp_setup(void)
|
|||
|
||||
static void __init cps_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
unsigned ncores, core_vpes, c;
|
||||
|
||||
mips_mt_set_cpuoptions();
|
||||
|
||||
/* Allocate core boot configuration structs */
|
||||
ncores = mips_cm_numcores();
|
||||
mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
|
||||
GFP_KERNEL);
|
||||
if (!mips_cps_core_bootcfg) {
|
||||
pr_err("Failed to allocate boot config for %u cores\n", ncores);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
/* Allocate VPE boot configuration structs */
|
||||
for (c = 0; c < ncores; c++) {
|
||||
core_vpes = core_vpe_count(c);
|
||||
mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
|
||||
sizeof(*mips_cps_core_bootcfg[c].vpe_config),
|
||||
GFP_KERNEL);
|
||||
if (!mips_cps_core_bootcfg[c].vpe_config) {
|
||||
pr_err("Failed to allocate %u VPE boot configs\n",
|
||||
core_vpes);
|
||||
goto err_out;
|
||||
}
|
||||
}
|
||||
|
||||
/* Mark this CPU as booted */
|
||||
atomic_set(&mips_cps_core_bootcfg[current_cpu_data.core].vpe_mask,
|
||||
1 << cpu_vpe_id(¤t_cpu_data));
|
||||
|
||||
return;
|
||||
err_out:
|
||||
/* Clean up allocations */
|
||||
if (mips_cps_core_bootcfg) {
|
||||
for (c = 0; c < ncores; c++)
|
||||
kfree(mips_cps_core_bootcfg[c].vpe_config);
|
||||
kfree(mips_cps_core_bootcfg);
|
||||
mips_cps_core_bootcfg = NULL;
|
||||
}
|
||||
|
||||
/* Effectively disable SMP by declaring CPUs not present */
|
||||
for_each_possible_cpu(c) {
|
||||
if (c == 0)
|
||||
continue;
|
||||
set_cpu_present(c, false);
|
||||
}
|
||||
}
|
||||
|
||||
static void boot_core(struct boot_config *cfg)
|
||||
static void boot_core(unsigned core)
|
||||
{
|
||||
u32 access;
|
||||
|
||||
/* Select the appropriate core */
|
||||
write_gcr_cl_other(cfg->core << CM_GCR_Cx_OTHER_CORENUM_SHF);
|
||||
write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
|
||||
|
||||
/* Set its reset vector */
|
||||
write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
|
||||
|
|
@ -175,15 +155,12 @@ static void boot_core(struct boot_config *cfg)
|
|||
|
||||
/* Ensure the core can access the GCRs */
|
||||
access = read_gcr_access();
|
||||
access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + cfg->core);
|
||||
access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core);
|
||||
write_gcr_access(access);
|
||||
|
||||
/* Copy cfg */
|
||||
mips_cps_bootcfg = *cfg;
|
||||
|
||||
if (mips_cpc_present()) {
|
||||
/* Select the appropriate core */
|
||||
write_cpc_cl_other(cfg->core << CPC_Cx_OTHER_CORENUM_SHF);
|
||||
write_cpc_cl_other(core << CPC_Cx_OTHER_CORENUM_SHF);
|
||||
|
||||
/* Reset the core */
|
||||
write_cpc_co_cmd(CPC_Cx_CMD_RESET);
|
||||
|
|
@ -193,77 +170,47 @@ static void boot_core(struct boot_config *cfg)
|
|||
}
|
||||
|
||||
/* The core is now powered up */
|
||||
bitmap_set(core_power, cfg->core, 1);
|
||||
bitmap_set(core_power, core, 1);
|
||||
}
|
||||
|
||||
static void boot_vpe(void *info)
|
||||
static void remote_vpe_boot(void *dummy)
|
||||
{
|
||||
struct boot_config *cfg = info;
|
||||
u32 tcstatus, vpeconf0;
|
||||
|
||||
/* Enter VPE configuration state */
|
||||
dvpe();
|
||||
set_c0_mvpcontrol(MVPCONTROL_VPC);
|
||||
|
||||
settc(cfg->vpe);
|
||||
|
||||
/* Set the TC restart PC */
|
||||
write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
|
||||
|
||||
/* Activate the TC, allow interrupts */
|
||||
tcstatus = read_tc_c0_tcstatus();
|
||||
tcstatus &= ~TCSTATUS_IXMT;
|
||||
tcstatus |= TCSTATUS_A;
|
||||
write_tc_c0_tcstatus(tcstatus);
|
||||
|
||||
/* Clear the TC halt bit */
|
||||
write_tc_c0_tchalt(0);
|
||||
|
||||
/* Activate the VPE */
|
||||
vpeconf0 = read_vpe_c0_vpeconf0();
|
||||
vpeconf0 |= VPECONF0_VPA;
|
||||
write_vpe_c0_vpeconf0(vpeconf0);
|
||||
|
||||
/* Set the stack & global pointer registers */
|
||||
write_tc_gpr_sp(cfg->sp);
|
||||
write_tc_gpr_gp(cfg->gp);
|
||||
|
||||
/* Leave VPE configuration state */
|
||||
clear_c0_mvpcontrol(MVPCONTROL_VPC);
|
||||
|
||||
/* Enable other VPEs to execute */
|
||||
evpe(EVPE_ENABLE);
|
||||
mips_cps_boot_vpes();
|
||||
}
|
||||
|
||||
static void cps_boot_secondary(int cpu, struct task_struct *idle)
|
||||
{
|
||||
struct boot_config cfg;
|
||||
unsigned core = cpu_data[cpu].core;
|
||||
unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
|
||||
struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
|
||||
struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
|
||||
unsigned int remote;
|
||||
int err;
|
||||
|
||||
cfg.core = cpu_data[cpu].core;
|
||||
cfg.vpe = cpu_vpe_id(&cpu_data[cpu]);
|
||||
cfg.pc = (unsigned long)&smp_bootstrap;
|
||||
cfg.sp = __KSTK_TOS(idle);
|
||||
cfg.gp = (unsigned long)task_thread_info(idle);
|
||||
vpe_cfg->pc = (unsigned long)&smp_bootstrap;
|
||||
vpe_cfg->sp = __KSTK_TOS(idle);
|
||||
vpe_cfg->gp = (unsigned long)task_thread_info(idle);
|
||||
|
||||
if (!test_bit(cfg.core, core_power)) {
|
||||
atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
|
||||
|
||||
if (!test_bit(core, core_power)) {
|
||||
/* Boot a VPE on a powered down core */
|
||||
boot_core(&cfg);
|
||||
boot_core(core);
|
||||
return;
|
||||
}
|
||||
|
||||
if (cfg.core != current_cpu_data.core) {
|
||||
if (core != current_cpu_data.core) {
|
||||
/* Boot a VPE on another powered up core */
|
||||
for (remote = 0; remote < NR_CPUS; remote++) {
|
||||
if (cpu_data[remote].core != cfg.core)
|
||||
if (cpu_data[remote].core != core)
|
||||
continue;
|
||||
if (cpu_online(remote))
|
||||
break;
|
||||
}
|
||||
BUG_ON(remote >= NR_CPUS);
|
||||
|
||||
err = smp_call_function_single(remote, boot_vpe, &cfg, 1);
|
||||
err = smp_call_function_single(remote, remote_vpe_boot,
|
||||
NULL, 1);
|
||||
if (err)
|
||||
panic("Failed to call remote CPU\n");
|
||||
return;
|
||||
|
|
@ -272,7 +219,7 @@ static void cps_boot_secondary(int cpu, struct task_struct *idle)
|
|||
BUG_ON(!cpu_has_mipsmt);
|
||||
|
||||
/* Boot a VPE on this core */
|
||||
boot_vpe(&cfg);
|
||||
mips_cps_boot_vpes();
|
||||
}
|
||||
|
||||
static void cps_init_secondary(void)
|
||||
|
|
@ -281,10 +228,6 @@ static void cps_init_secondary(void)
|
|||
if (cpu_has_mipsmt)
|
||||
dmt();
|
||||
|
||||
/* TODO: revisit this assumption once hotplug is implemented */
|
||||
if (cpu_vpe_id(¤t_cpu_data) == 0)
|
||||
init_core();
|
||||
|
||||
change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
|
||||
STATUSF_IP6 | STATUSF_IP7);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue