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mmc: renesas_sdhi: add eMMC HS400 mode support
This patch adds processing for selecting HS400 mode. Signed-off-by: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Masaharu Hayakawa
Ulf Hansson
parent
db924bba47
commit
26eb2607fa
3 changed files with 138 additions and 26 deletions
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@ -212,6 +212,7 @@ static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
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#define SH_MOBILE_SDHI_SCC_CKSEL 0x006
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#define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008
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#define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A
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#define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E
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/* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */
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#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0)
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@ -224,6 +225,9 @@ static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
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#define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
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/* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */
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#define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2)
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/* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT2 register */
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#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
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#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
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static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
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struct renesas_sdhi *priv, int addr)
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@ -244,33 +248,30 @@ static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
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priv = host_to_priv(host);
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/* set sampling clock selection range */
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
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0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
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/* Initialize SCC */
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sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
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SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL));
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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/* set sampling clock selection range */
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
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SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
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0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
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SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
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~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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/* Read TAPNUM */
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return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
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SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
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@ -286,13 +287,95 @@ static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host *host,
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap);
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}
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static void renesas_sdhi_hs400_complete(struct tmio_mmc_host *host)
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{
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struct renesas_sdhi *priv = host_to_priv(host);
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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/* Set HS400 mode */
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sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 |
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sd_ctrl_read16(host, CTL_SDIF_MODE));
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
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(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
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SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
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/* Set the sampling clock selection range of HS400 mode */
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
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SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
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0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
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if (host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400)
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
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host->tap_set / 2);
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
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SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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}
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static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host,
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struct renesas_sdhi *priv)
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{
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
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~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
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sd_scc_read32(host, priv,
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SH_MOBILE_SDHI_SCC_CKSEL));
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}
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static void renesas_sdhi_disable_scc(struct tmio_mmc_host *host)
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{
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struct renesas_sdhi *priv = host_to_priv(host);
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renesas_sdhi_reset_scc(host, priv);
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
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~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
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sd_scc_read32(host, priv,
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SH_MOBILE_SDHI_SCC_DTCNTL));
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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}
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static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
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struct renesas_sdhi *priv)
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{
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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/* Reset HS400 mode */
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sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 &
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sd_ctrl_read16(host, CTL_SDIF_MODE));
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
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~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
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SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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}
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static void renesas_sdhi_prepare_hs400_tuning(struct tmio_mmc_host *host)
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{
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renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
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}
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#define SH_MOBILE_SDHI_MAX_TAP 3
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static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
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{
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struct renesas_sdhi *priv = host_to_priv(host);
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unsigned long tap_cnt; /* counter of tuning success */
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unsigned long tap_set; /* tap position */
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unsigned long tap_start;/* start position of tuning success */
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unsigned long tap_end; /* end position of tuning success */
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unsigned long ntap; /* temporary counter of tuning success */
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@ -330,12 +413,12 @@ static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
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}
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if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP)
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tap_set = (tap_start + tap_end) / 2 % host->tap_num;
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host->tap_set = (tap_start + tap_end) / 2 % host->tap_num;
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else
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return -EIO;
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/* Set SCC */
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap_set);
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, host->tap_set);
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/* Enable auto re-tuning */
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
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@ -368,13 +451,8 @@ static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host)
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priv = host_to_priv(host);
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/* Reset SCC */
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
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~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
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renesas_sdhi_reset_scc(host, priv);
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renesas_sdhi_reset_hs400_mode(host, priv);
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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@ -592,7 +670,8 @@ int renesas_sdhi_probe(struct platform_device *pdev,
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/* Enable tuning iff we have an SCC and a supported mode */
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if (of_data && of_data->scc_offset &&
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(host->mmc->caps & MMC_CAP_UHS_SDR104 ||
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host->mmc->caps2 & MMC_CAP2_HS200_1_8V_SDR)) {
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host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
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MMC_CAP2_HS400_1_8V))) {
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const struct renesas_sdhi_scc *taps = of_data->taps;
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bool hit = false;
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@ -616,6 +695,10 @@ int renesas_sdhi_probe(struct platform_device *pdev,
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host->select_tuning = renesas_sdhi_select_tuning;
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host->check_scc_error = renesas_sdhi_check_scc_error;
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host->hw_reset = renesas_sdhi_hw_reset;
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host->prepare_hs400_tuning =
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renesas_sdhi_prepare_hs400_tuning;
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host->hs400_downgrade = renesas_sdhi_disable_scc;
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host->hs400_complete = renesas_sdhi_hs400_complete;
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}
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i = 0;
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@ -82,6 +82,22 @@ static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
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},
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};
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static const struct renesas_sdhi_of_data of_rcar_r8a7795_compatible = {
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
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TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 |
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TMIO_MMC_HAVE_4TAP_HS400,
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
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MMC_CAP_CMD23,
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.capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
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.bus_shift = 2,
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.scc_offset = 0x1000,
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.taps = rcar_gen3_scc_taps,
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.taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
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/* DMAC can handle 0xffffffff blk count but only 1 segment */
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.max_blk_count = 0xffffffff,
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.max_segs = 1,
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};
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static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
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TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
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@ -98,8 +114,8 @@ static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
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};
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static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
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{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
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{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
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{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_r8a7795_compatible, },
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{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_r8a7795_compatible, },
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{ .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
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{},
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};
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@ -78,6 +78,19 @@ static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
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},
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};
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static const struct renesas_sdhi_of_data of_rcar_r8a7795_compatible = {
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
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TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 |
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TMIO_MMC_HAVE_4TAP_HS400,
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
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MMC_CAP_CMD23,
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.capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
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.bus_shift = 2,
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.scc_offset = 0x1000,
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.taps = rcar_gen3_scc_taps,
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.taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
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};
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static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
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TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
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@ -104,8 +117,8 @@ static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {
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{ .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, },
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{ .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, },
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{ .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, },
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{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
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{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
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{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_r8a7795_compatible, },
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{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_r8a7795_compatible, },
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{ .compatible = "renesas,rcar-gen1-sdhi", .data = &of_rcar_gen1_compatible, },
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{ .compatible = "renesas,rcar-gen2-sdhi", .data = &of_rcar_gen2_compatible, },
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{ .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
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