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clk: at91: rework main clk implementation
AT91 main clk is a clk multiplexer and not a simple fixed rate clk as currently implemented. In some SoCs (sam9x5, sama5, sam9g45 families) this multiplexer can choose among 2 sources: an internal RC oscillator circuit and an oscillator using an external crystal. In other Socs (sam9260, rm9200 families) the multiplexer source is hardcoded to the external crystal oscillator. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This commit is contained in:
Boris BREZILLON
Nicolas Ferre
parent
cf2e933ce6
commit
27cb1c2083
3 changed files with 543 additions and 74 deletions
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@ -30,99 +30,412 @@
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#define MAINF_LOOP_MIN_WAIT (USEC_PER_SEC / SLOW_CLOCK_FREQ)
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#define MAINF_LOOP_MAX_WAIT MAINFRDY_TIMEOUT
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struct clk_main {
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#define MOR_KEY_MASK (0xff << 16)
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struct clk_main_osc {
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struct clk_hw hw;
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struct at91_pmc *pmc;
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unsigned long rate;
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unsigned int irq;
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wait_queue_head_t wait;
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};
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#define to_clk_main(hw) container_of(hw, struct clk_main, hw)
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#define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)
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static irqreturn_t clk_main_irq_handler(int irq, void *dev_id)
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struct clk_main_rc_osc {
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struct clk_hw hw;
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struct at91_pmc *pmc;
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unsigned int irq;
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wait_queue_head_t wait;
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unsigned long frequency;
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unsigned long accuracy;
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};
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#define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)
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struct clk_rm9200_main {
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struct clk_hw hw;
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struct at91_pmc *pmc;
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};
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#define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw)
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struct clk_sam9x5_main {
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struct clk_hw hw;
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struct at91_pmc *pmc;
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unsigned int irq;
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wait_queue_head_t wait;
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u8 parent;
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};
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#define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw)
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static irqreturn_t clk_main_osc_irq_handler(int irq, void *dev_id)
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{
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struct clk_main *clkmain = (struct clk_main *)dev_id;
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struct clk_main_osc *osc = dev_id;
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wake_up(&clkmain->wait);
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disable_irq_nosync(clkmain->irq);
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wake_up(&osc->wait);
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disable_irq_nosync(osc->irq);
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return IRQ_HANDLED;
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}
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static int clk_main_prepare(struct clk_hw *hw)
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static int clk_main_osc_prepare(struct clk_hw *hw)
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{
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struct clk_main *clkmain = to_clk_main(hw);
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struct at91_pmc *pmc = clkmain->pmc;
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unsigned long halt_time, timeout;
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struct clk_main_osc *osc = to_clk_main_osc(hw);
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struct at91_pmc *pmc = osc->pmc;
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u32 tmp;
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while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS)) {
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enable_irq(clkmain->irq);
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wait_event(clkmain->wait,
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pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS);
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}
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if (clkmain->rate)
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tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK;
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if (tmp & AT91_PMC_OSCBYPASS)
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return 0;
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timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT);
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do {
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halt_time = jiffies;
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tmp = pmc_read(pmc, AT91_CKGR_MCFR);
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if (tmp & AT91_PMC_MAINRDY)
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return 0;
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usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
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} while (time_before(halt_time, timeout));
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if (!(tmp & AT91_PMC_MOSCEN)) {
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tmp |= AT91_PMC_MOSCEN | AT91_PMC_KEY;
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pmc_write(pmc, AT91_CKGR_MOR, tmp);
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}
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while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS)) {
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enable_irq(osc->irq);
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wait_event(osc->wait,
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pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS);
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}
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return 0;
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}
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static int clk_main_is_prepared(struct clk_hw *hw)
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static void clk_main_osc_unprepare(struct clk_hw *hw)
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{
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struct clk_main *clkmain = to_clk_main(hw);
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struct clk_main_osc *osc = to_clk_main_osc(hw);
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struct at91_pmc *pmc = osc->pmc;
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u32 tmp = pmc_read(pmc, AT91_CKGR_MOR);
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return !!(pmc_read(clkmain->pmc, AT91_PMC_SR) & AT91_PMC_MOSCS);
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if (tmp & AT91_PMC_OSCBYPASS)
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return;
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if (!(tmp & AT91_PMC_MOSCEN))
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return;
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tmp &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN);
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pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_KEY);
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}
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static unsigned long clk_main_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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static int clk_main_osc_is_prepared(struct clk_hw *hw)
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{
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u32 tmp;
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struct clk_main *clkmain = to_clk_main(hw);
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struct at91_pmc *pmc = clkmain->pmc;
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struct clk_main_osc *osc = to_clk_main_osc(hw);
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struct at91_pmc *pmc = osc->pmc;
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u32 tmp = pmc_read(pmc, AT91_CKGR_MOR);
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if (clkmain->rate)
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return clkmain->rate;
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if (tmp & AT91_PMC_OSCBYPASS)
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return 1;
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tmp = pmc_read(pmc, AT91_CKGR_MCFR) & AT91_PMC_MAINF;
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clkmain->rate = (tmp * parent_rate) / MAINF_DIV;
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return clkmain->rate;
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return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS) &&
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(pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN));
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}
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static const struct clk_ops main_ops = {
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.prepare = clk_main_prepare,
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.is_prepared = clk_main_is_prepared,
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.recalc_rate = clk_main_recalc_rate,
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static const struct clk_ops main_osc_ops = {
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.prepare = clk_main_osc_prepare,
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.unprepare = clk_main_osc_unprepare,
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.is_prepared = clk_main_osc_is_prepared,
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};
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static struct clk * __init
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at91_clk_register_main(struct at91_pmc *pmc,
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unsigned int irq,
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const char *name,
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const char *parent_name,
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unsigned long rate)
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at91_clk_register_main_osc(struct at91_pmc *pmc,
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unsigned int irq,
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const char *name,
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const char *parent_name,
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bool bypass)
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{
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int ret;
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struct clk_main *clkmain;
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struct clk_main_osc *osc;
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struct clk *clk = NULL;
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struct clk_init_data init;
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if (!pmc || !irq || !name)
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if (!pmc || !irq || !name || !parent_name)
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return ERR_PTR(-EINVAL);
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if (!rate && !parent_name)
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osc = kzalloc(sizeof(*osc), GFP_KERNEL);
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if (!osc)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &main_osc_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.flags = CLK_IGNORE_UNUSED;
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osc->hw.init = &init;
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osc->pmc = pmc;
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osc->irq = irq;
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init_waitqueue_head(&osc->wait);
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irq_set_status_flags(osc->irq, IRQ_NOAUTOEN);
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ret = request_irq(osc->irq, clk_main_osc_irq_handler,
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IRQF_TRIGGER_HIGH, name, osc);
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if (ret)
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return ERR_PTR(ret);
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if (bypass)
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pmc_write(pmc, AT91_CKGR_MOR,
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(pmc_read(pmc, AT91_CKGR_MOR) &
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~(MOR_KEY_MASK | AT91_PMC_MOSCEN)) |
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AT91_PMC_OSCBYPASS | AT91_PMC_KEY);
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clk = clk_register(NULL, &osc->hw);
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if (IS_ERR(clk)) {
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free_irq(irq, osc);
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kfree(osc);
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}
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return clk;
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}
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void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np,
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struct at91_pmc *pmc)
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{
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struct clk *clk;
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unsigned int irq;
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const char *name = np->name;
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const char *parent_name;
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bool bypass;
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of_property_read_string(np, "clock-output-names", &name);
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bypass = of_property_read_bool(np, "atmel,osc-bypass");
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parent_name = of_clk_get_parent_name(np, 0);
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irq = irq_of_parse_and_map(np, 0);
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if (!irq)
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return;
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clk = at91_clk_register_main_osc(pmc, irq, name, parent_name, bypass);
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if (IS_ERR(clk))
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return;
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of_clk_add_provider(np, of_clk_src_simple_get, clk);
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}
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static irqreturn_t clk_main_rc_osc_irq_handler(int irq, void *dev_id)
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{
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struct clk_main_rc_osc *osc = dev_id;
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wake_up(&osc->wait);
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disable_irq_nosync(osc->irq);
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return IRQ_HANDLED;
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}
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static int clk_main_rc_osc_prepare(struct clk_hw *hw)
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{
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struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
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struct at91_pmc *pmc = osc->pmc;
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u32 tmp;
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tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK;
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if (!(tmp & AT91_PMC_MOSCRCEN)) {
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tmp |= AT91_PMC_MOSCRCEN | AT91_PMC_KEY;
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pmc_write(pmc, AT91_CKGR_MOR, tmp);
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}
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while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS)) {
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enable_irq(osc->irq);
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wait_event(osc->wait,
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pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS);
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}
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return 0;
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}
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static void clk_main_rc_osc_unprepare(struct clk_hw *hw)
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{
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struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
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struct at91_pmc *pmc = osc->pmc;
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u32 tmp = pmc_read(pmc, AT91_CKGR_MOR);
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if (!(tmp & AT91_PMC_MOSCRCEN))
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return;
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tmp &= ~(MOR_KEY_MASK | AT91_PMC_MOSCRCEN);
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pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_KEY);
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}
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static int clk_main_rc_osc_is_prepared(struct clk_hw *hw)
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{
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struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
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struct at91_pmc *pmc = osc->pmc;
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return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS) &&
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(pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCRCEN));
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}
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static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
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return osc->frequency;
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}
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static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw,
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unsigned long parent_acc)
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{
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struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
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return osc->accuracy;
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}
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static const struct clk_ops main_rc_osc_ops = {
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.prepare = clk_main_rc_osc_prepare,
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.unprepare = clk_main_rc_osc_unprepare,
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.is_prepared = clk_main_rc_osc_is_prepared,
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.recalc_rate = clk_main_rc_osc_recalc_rate,
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.recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
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};
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static struct clk * __init
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at91_clk_register_main_rc_osc(struct at91_pmc *pmc,
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unsigned int irq,
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const char *name,
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u32 frequency, u32 accuracy)
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{
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int ret;
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struct clk_main_rc_osc *osc;
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struct clk *clk = NULL;
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struct clk_init_data init;
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if (!pmc || !irq || !name || !frequency)
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return ERR_PTR(-EINVAL);
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osc = kzalloc(sizeof(*osc), GFP_KERNEL);
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if (!osc)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &main_rc_osc_ops;
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init.parent_names = NULL;
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init.num_parents = 0;
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init.flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED;
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osc->hw.init = &init;
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osc->pmc = pmc;
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osc->irq = irq;
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osc->frequency = frequency;
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osc->accuracy = accuracy;
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init_waitqueue_head(&osc->wait);
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irq_set_status_flags(osc->irq, IRQ_NOAUTOEN);
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ret = request_irq(osc->irq, clk_main_rc_osc_irq_handler,
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IRQF_TRIGGER_HIGH, name, osc);
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if (ret)
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return ERR_PTR(ret);
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clk = clk_register(NULL, &osc->hw);
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if (IS_ERR(clk)) {
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free_irq(irq, osc);
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kfree(osc);
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}
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return clk;
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}
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void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np,
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struct at91_pmc *pmc)
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{
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struct clk *clk;
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unsigned int irq;
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u32 frequency = 0;
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u32 accuracy = 0;
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const char *name = np->name;
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of_property_read_string(np, "clock-output-names", &name);
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of_property_read_u32(np, "clock-frequency", &frequency);
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of_property_read_u32(np, "clock-accuracy", &accuracy);
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irq = irq_of_parse_and_map(np, 0);
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if (!irq)
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return;
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clk = at91_clk_register_main_rc_osc(pmc, irq, name, frequency,
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accuracy);
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if (IS_ERR(clk))
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return;
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of_clk_add_provider(np, of_clk_src_simple_get, clk);
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}
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static int clk_main_probe_frequency(struct at91_pmc *pmc)
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{
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unsigned long prep_time, timeout;
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u32 tmp;
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timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT);
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do {
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prep_time = jiffies;
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tmp = pmc_read(pmc, AT91_CKGR_MCFR);
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if (tmp & AT91_PMC_MAINRDY)
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return 0;
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usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
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} while (time_before(prep_time, timeout));
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return -ETIMEDOUT;
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}
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static unsigned long clk_main_recalc_rate(struct at91_pmc *pmc,
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unsigned long parent_rate)
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{
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u32 tmp;
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if (parent_rate)
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return parent_rate;
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tmp = pmc_read(pmc, AT91_CKGR_MCFR);
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if (!(tmp & AT91_PMC_MAINRDY))
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return 0;
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return ((tmp & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV;
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}
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static int clk_rm9200_main_prepare(struct clk_hw *hw)
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{
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struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
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return clk_main_probe_frequency(clkmain->pmc);
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}
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static int clk_rm9200_main_is_prepared(struct clk_hw *hw)
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{
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struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
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return !!(pmc_read(clkmain->pmc, AT91_CKGR_MCFR) & AT91_PMC_MAINRDY);
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}
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static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
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return clk_main_recalc_rate(clkmain->pmc, parent_rate);
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}
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|
||||
static const struct clk_ops rm9200_main_ops = {
|
||||
.prepare = clk_rm9200_main_prepare,
|
||||
.is_prepared = clk_rm9200_main_is_prepared,
|
||||
.recalc_rate = clk_rm9200_main_recalc_rate,
|
||||
};
|
||||
|
||||
static struct clk * __init
|
||||
at91_clk_register_rm9200_main(struct at91_pmc *pmc,
|
||||
const char *name,
|
||||
const char *parent_name)
|
||||
{
|
||||
struct clk_rm9200_main *clkmain;
|
||||
struct clk *clk = NULL;
|
||||
struct clk_init_data init;
|
||||
|
||||
if (!pmc || !name)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
if (!parent_name)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
|
||||
|
|
@ -130,19 +443,154 @@ at91_clk_register_main(struct at91_pmc *pmc,
|
|||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.ops = &main_ops;
|
||||
init.parent_names = parent_name ? &parent_name : NULL;
|
||||
init.num_parents = parent_name ? 1 : 0;
|
||||
init.flags = parent_name ? 0 : CLK_IS_ROOT;
|
||||
init.ops = &rm9200_main_ops;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
init.flags = 0;
|
||||
|
||||
clkmain->hw.init = &init;
|
||||
clkmain->pmc = pmc;
|
||||
|
||||
clk = clk_register(NULL, &clkmain->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(clkmain);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
void __init of_at91rm9200_clk_main_setup(struct device_node *np,
|
||||
struct at91_pmc *pmc)
|
||||
{
|
||||
struct clk *clk;
|
||||
const char *parent_name;
|
||||
const char *name = np->name;
|
||||
|
||||
parent_name = of_clk_get_parent_name(np, 0);
|
||||
of_property_read_string(np, "clock-output-names", &name);
|
||||
|
||||
clk = at91_clk_register_rm9200_main(pmc, name, parent_name);
|
||||
if (IS_ERR(clk))
|
||||
return;
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
||||
}
|
||||
|
||||
static irqreturn_t clk_sam9x5_main_irq_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct clk_sam9x5_main *clkmain = dev_id;
|
||||
|
||||
wake_up(&clkmain->wait);
|
||||
disable_irq_nosync(clkmain->irq);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int clk_sam9x5_main_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
|
||||
struct at91_pmc *pmc = clkmain->pmc;
|
||||
|
||||
while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) {
|
||||
enable_irq(clkmain->irq);
|
||||
wait_event(clkmain->wait,
|
||||
pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS);
|
||||
}
|
||||
|
||||
return clk_main_probe_frequency(pmc);
|
||||
}
|
||||
|
||||
static int clk_sam9x5_main_is_prepared(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
|
||||
|
||||
return !!(pmc_read(clkmain->pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS);
|
||||
}
|
||||
|
||||
static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
|
||||
|
||||
return clk_main_recalc_rate(clkmain->pmc, parent_rate);
|
||||
}
|
||||
|
||||
static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
|
||||
struct at91_pmc *pmc = clkmain->pmc;
|
||||
u32 tmp;
|
||||
|
||||
if (index > 1)
|
||||
return -EINVAL;
|
||||
|
||||
tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK;
|
||||
|
||||
if (index && !(tmp & AT91_PMC_MOSCSEL))
|
||||
pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_MOSCSEL);
|
||||
else if (!index && (tmp & AT91_PMC_MOSCSEL))
|
||||
pmc_write(pmc, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL);
|
||||
|
||||
while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) {
|
||||
enable_irq(clkmain->irq);
|
||||
wait_event(clkmain->wait,
|
||||
pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
|
||||
|
||||
return !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN);
|
||||
}
|
||||
|
||||
static const struct clk_ops sam9x5_main_ops = {
|
||||
.prepare = clk_sam9x5_main_prepare,
|
||||
.is_prepared = clk_sam9x5_main_is_prepared,
|
||||
.recalc_rate = clk_sam9x5_main_recalc_rate,
|
||||
.set_parent = clk_sam9x5_main_set_parent,
|
||||
.get_parent = clk_sam9x5_main_get_parent,
|
||||
};
|
||||
|
||||
static struct clk * __init
|
||||
at91_clk_register_sam9x5_main(struct at91_pmc *pmc,
|
||||
unsigned int irq,
|
||||
const char *name,
|
||||
const char **parent_names,
|
||||
int num_parents)
|
||||
{
|
||||
int ret;
|
||||
struct clk_sam9x5_main *clkmain;
|
||||
struct clk *clk = NULL;
|
||||
struct clk_init_data init;
|
||||
|
||||
if (!pmc || !irq || !name)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
if (!parent_names || !num_parents)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
|
||||
if (!clkmain)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.ops = &sam9x5_main_ops;
|
||||
init.parent_names = parent_names;
|
||||
init.num_parents = num_parents;
|
||||
init.flags = CLK_SET_PARENT_GATE;
|
||||
|
||||
clkmain->hw.init = &init;
|
||||
clkmain->rate = rate;
|
||||
clkmain->pmc = pmc;
|
||||
clkmain->irq = irq;
|
||||
clkmain->parent = !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) &
|
||||
AT91_PMC_MOSCEN);
|
||||
init_waitqueue_head(&clkmain->wait);
|
||||
irq_set_status_flags(clkmain->irq, IRQ_NOAUTOEN);
|
||||
ret = request_irq(clkmain->irq, clk_main_irq_handler,
|
||||
IRQF_TRIGGER_HIGH, "clk-main", clkmain);
|
||||
ret = request_irq(clkmain->irq, clk_sam9x5_main_irq_handler,
|
||||
IRQF_TRIGGER_HIGH, name, clkmain);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
|
|
@ -155,33 +603,36 @@ at91_clk_register_main(struct at91_pmc *pmc,
|
|||
return clk;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void __init
|
||||
of_at91_clk_main_setup(struct device_node *np, struct at91_pmc *pmc)
|
||||
void __init of_at91sam9x5_clk_main_setup(struct device_node *np,
|
||||
struct at91_pmc *pmc)
|
||||
{
|
||||
struct clk *clk;
|
||||
const char *parent_names[2];
|
||||
int num_parents;
|
||||
unsigned int irq;
|
||||
const char *parent_name;
|
||||
const char *name = np->name;
|
||||
u32 rate = 0;
|
||||
int i;
|
||||
|
||||
num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
|
||||
if (num_parents <= 0 || num_parents > 2)
|
||||
return;
|
||||
|
||||
for (i = 0; i < num_parents; ++i) {
|
||||
parent_names[i] = of_clk_get_parent_name(np, i);
|
||||
if (!parent_names[i])
|
||||
return;
|
||||
}
|
||||
|
||||
parent_name = of_clk_get_parent_name(np, 0);
|
||||
of_property_read_string(np, "clock-output-names", &name);
|
||||
of_property_read_u32(np, "clock-frequency", &rate);
|
||||
|
||||
irq = irq_of_parse_and_map(np, 0);
|
||||
if (!irq)
|
||||
return;
|
||||
|
||||
clk = at91_clk_register_main(pmc, irq, name, parent_name, rate);
|
||||
clk = at91_clk_register_sam9x5_main(pmc, irq, name, parent_names,
|
||||
num_parents);
|
||||
if (IS_ERR(clk))
|
||||
return;
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
||||
}
|
||||
|
||||
void __init of_at91rm9200_clk_main_setup(struct device_node *np,
|
||||
struct at91_pmc *pmc)
|
||||
{
|
||||
of_at91_clk_main_setup(np, pmc);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -230,10 +230,22 @@ static struct at91_pmc *__init at91_pmc_init(struct device_node *np,
|
|||
|
||||
static const struct of_device_id pmc_clk_ids[] __initconst = {
|
||||
/* Main clock */
|
||||
{
|
||||
.compatible = "atmel,at91rm9200-clk-main-osc",
|
||||
.data = of_at91rm9200_clk_main_osc_setup,
|
||||
},
|
||||
{
|
||||
.compatible = "atmel,at91sam9x5-clk-main-rc-osc",
|
||||
.data = of_at91sam9x5_clk_main_rc_osc_setup,
|
||||
},
|
||||
{
|
||||
.compatible = "atmel,at91rm9200-clk-main",
|
||||
.data = of_at91rm9200_clk_main_setup,
|
||||
},
|
||||
{
|
||||
.compatible = "atmel,at91sam9x5-clk-main",
|
||||
.data = of_at91sam9x5_clk_main_setup,
|
||||
},
|
||||
/* PLL clocks */
|
||||
{
|
||||
.compatible = "atmel,at91rm9200-clk-pll",
|
||||
|
|
|
|||
|
|
@ -58,8 +58,14 @@ static inline void pmc_write(struct at91_pmc *pmc, int offset, u32 value)
|
|||
int of_at91_get_clk_range(struct device_node *np, const char *propname,
|
||||
struct clk_range *range);
|
||||
|
||||
extern void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np,
|
||||
struct at91_pmc *pmc);
|
||||
extern void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np,
|
||||
struct at91_pmc *pmc);
|
||||
extern void __init of_at91rm9200_clk_main_setup(struct device_node *np,
|
||||
struct at91_pmc *pmc);
|
||||
extern void __init of_at91sam9x5_clk_main_setup(struct device_node *np,
|
||||
struct at91_pmc *pmc);
|
||||
|
||||
extern void __init of_at91rm9200_clk_pll_setup(struct device_node *np,
|
||||
struct at91_pmc *pmc);
|
||||
|
|
|
|||
Loading…
Reference in a new issue