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crypto: caam/jr - add support for DPAA2 parts
Add support for using the caam/jr backend on DPAA2-based SoCs. These have some particularities we have to account for: -HW S/G format is different -Management Complex (MC) firmware initializes / manages (partially) the CAAM block: MCFGR, QI enablement in QICTL, RNG Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Horia Geantă
Herbert Xu
parent
e28c190db6
commit
297b9cebd2
7 changed files with 148 additions and 25 deletions
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@ -791,8 +791,8 @@ static int ahash_update_ctx(struct ahash_request *req)
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to_hash - *buflen,
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*next_buflen, 0);
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} else {
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(edesc->sec4_sg + sec4_sg_src_index - 1)->len |=
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cpu_to_caam32(SEC4_SG_LEN_FIN);
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sg_to_sec4_set_last(edesc->sec4_sg + sec4_sg_src_index -
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1);
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}
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desc = edesc->hw_desc;
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@ -882,8 +882,7 @@ static int ahash_final_ctx(struct ahash_request *req)
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if (ret)
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goto unmap_ctx;
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(edesc->sec4_sg + sec4_sg_src_index - 1)->len |=
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cpu_to_caam32(SEC4_SG_LEN_FIN);
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sg_to_sec4_set_last(edesc->sec4_sg + sec4_sg_src_index - 1);
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edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
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sec4_sg_bytes, DMA_TO_DEVICE);
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@ -17,6 +17,8 @@
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bool caam_little_end;
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EXPORT_SYMBOL(caam_little_end);
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bool caam_dpaa2;
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EXPORT_SYMBOL(caam_dpaa2);
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#ifdef CONFIG_CAAM_QI
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#include "qi.h"
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@ -319,8 +321,11 @@ static int caam_remove(struct platform_device *pdev)
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caam_qi_shutdown(ctrlpriv->qidev);
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#endif
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/* De-initialize RNG state handles initialized by this driver. */
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if (ctrlpriv->rng4_sh_init)
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/*
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* De-initialize RNG state handles initialized by this driver.
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* In case of DPAA 2.x, RNG is managed by MC firmware.
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*/
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if (!caam_dpaa2 && ctrlpriv->rng4_sh_init)
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deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
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/* Shut down debug views */
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@ -552,12 +557,17 @@ static int caam_probe(struct platform_device *pdev)
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/*
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* Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
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* long pointers in master configuration register
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* long pointers in master configuration register.
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* In case of DPAA 2.x, Management Complex firmware performs
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* the configuration.
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*/
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clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR,
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MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
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MCFGR_WDENABLE | MCFGR_LARGE_BURST |
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(sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
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caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
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if (!caam_dpaa2)
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clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR,
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MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
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MCFGR_WDENABLE | MCFGR_LARGE_BURST |
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(sizeof(dma_addr_t) == sizeof(u64) ?
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MCFGR_LONG_PTR : 0));
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/*
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* Read the Compile Time paramters and SCFGR to determine
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@ -586,7 +596,9 @@ static int caam_probe(struct platform_device *pdev)
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JRSTART_JR3_START);
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if (sizeof(dma_addr_t) == sizeof(u64)) {
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if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
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if (caam_dpaa2)
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(49));
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else if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
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else
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
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@ -629,11 +641,9 @@ static int caam_probe(struct platform_device *pdev)
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ring++;
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}
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/* Check to see if QI present. If so, enable */
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ctrlpriv->qi_present =
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!!(rd_reg32(&ctrl->perfmon.comp_parms_ms) &
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CTPR_MS_QI_MASK);
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if (ctrlpriv->qi_present) {
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/* Check to see if (DPAA 1.x) QI present. If so, enable */
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ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
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if (ctrlpriv->qi_present && !caam_dpaa2) {
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ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
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((__force uint8_t *)ctrl +
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BLOCK_OFFSET * QI_BLOCK_NUMBER
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@ -661,8 +671,10 @@ static int caam_probe(struct platform_device *pdev)
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/*
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* If SEC has RNG version >= 4 and RNG state handle has not been
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* already instantiated, do RNG instantiation
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* In case of DPAA 2.x, RNG is managed by MC firmware.
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*/
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if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
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if (!caam_dpaa2 &&
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(cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
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ctrlpriv->rng4_sh_init =
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rd_reg32(&ctrl->r4tst[0].rdsta);
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/*
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@ -730,8 +742,9 @@ static int caam_probe(struct platform_device *pdev)
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/* Report "alive" for developer to see */
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dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
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caam_get_era());
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dev_info(dev, "job rings = %d, qi = %d\n",
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ctrlpriv->total_jobrs, ctrlpriv->qi_present);
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dev_info(dev, "job rings = %d, qi = %d, dpaa2 = %s\n",
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ctrlpriv->total_jobrs, ctrlpriv->qi_present,
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caam_dpaa2 ? "yes" : "no");
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#ifdef CONFIG_DEBUG_FS
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@ -10,4 +10,6 @@
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/* Prototypes for backend-level services exposed to APIs */
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int caam_get_era(void);
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extern bool caam_dpaa2;
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#endif /* CTRL_H */
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@ -9,6 +9,7 @@
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#include <linux/of_address.h>
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#include "compat.h"
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#include "ctrl.h"
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#include "regs.h"
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#include "jr.h"
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#include "desc.h"
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@ -499,7 +500,11 @@ static int caam_jr_probe(struct platform_device *pdev)
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jrpriv->rregs = (struct caam_job_ring __iomem __force *)ctrl;
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if (sizeof(dma_addr_t) == sizeof(u64)) {
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if (of_device_is_compatible(nprop, "fsl,sec-v5.0-job-ring"))
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if (caam_dpaa2)
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error = dma_set_mask_and_coherent(jrdev,
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DMA_BIT_MASK(49));
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else if (of_device_is_compatible(nprop,
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"fsl,sec-v5.0-job-ring"))
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error = dma_set_mask_and_coherent(jrdev,
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DMA_BIT_MASK(40));
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else
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@ -293,6 +293,7 @@ struct caam_perfmon {
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u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/
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#define CTPR_MS_QI_SHIFT 25
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#define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT)
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#define CTPR_MS_DPAA2 BIT(13)
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#define CTPR_MS_VIRT_EN_INCL 0x00000001
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#define CTPR_MS_VIRT_EN_POR 0x00000002
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#define CTPR_MS_PG_SZ_MASK 0x10
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81
drivers/crypto/caam/sg_sw_qm2.h
Normal file
81
drivers/crypto/caam/sg_sw_qm2.h
Normal file
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@ -0,0 +1,81 @@
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/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the names of the above-listed copyright holders nor the
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* names of any contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SG_SW_QM2_H_
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#define _SG_SW_QM2_H_
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#include "../../../drivers/staging/fsl-mc/include/dpaa2-fd.h"
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static inline void dma_to_qm_sg_one(struct dpaa2_sg_entry *qm_sg_ptr,
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dma_addr_t dma, u32 len, u16 offset)
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{
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dpaa2_sg_set_addr(qm_sg_ptr, dma);
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dpaa2_sg_set_format(qm_sg_ptr, dpaa2_sg_single);
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dpaa2_sg_set_final(qm_sg_ptr, false);
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dpaa2_sg_set_len(qm_sg_ptr, len);
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dpaa2_sg_set_bpid(qm_sg_ptr, 0);
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dpaa2_sg_set_offset(qm_sg_ptr, offset);
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}
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/*
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* convert scatterlist to h/w link table format
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* but does not have final bit; instead, returns last entry
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*/
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static inline struct dpaa2_sg_entry *
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sg_to_qm_sg(struct scatterlist *sg, int sg_count,
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struct dpaa2_sg_entry *qm_sg_ptr, u16 offset)
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{
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while (sg_count && sg) {
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dma_to_qm_sg_one(qm_sg_ptr, sg_dma_address(sg),
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sg_dma_len(sg), offset);
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qm_sg_ptr++;
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sg = sg_next(sg);
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sg_count--;
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}
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return qm_sg_ptr - 1;
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}
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/*
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* convert scatterlist to h/w link table format
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* scatterlist must have been previously dma mapped
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*/
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static inline void sg_to_qm_sg_last(struct scatterlist *sg, int sg_count,
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struct dpaa2_sg_entry *qm_sg_ptr,
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u16 offset)
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{
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qm_sg_ptr = sg_to_qm_sg(sg, sg_count, qm_sg_ptr, offset);
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dpaa2_sg_set_final(qm_sg_ptr, true);
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}
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#endif /* _SG_SW_QM2_H_ */
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@ -5,7 +5,13 @@
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*
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*/
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#ifndef _SG_SW_SEC4_H_
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#define _SG_SW_SEC4_H_
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#include "ctrl.h"
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#include "regs.h"
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#include "sg_sw_qm2.h"
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#include "../../../drivers/staging/fsl-mc/include/dpaa2-fd.h"
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struct sec4_sg_entry {
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u64 ptr;
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@ -19,9 +25,15 @@ struct sec4_sg_entry {
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static inline void dma_to_sec4_sg_one(struct sec4_sg_entry *sec4_sg_ptr,
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dma_addr_t dma, u32 len, u16 offset)
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{
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sec4_sg_ptr->ptr = cpu_to_caam_dma64(dma);
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sec4_sg_ptr->len = cpu_to_caam32(len);
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sec4_sg_ptr->bpid_offset = cpu_to_caam32(offset & SEC4_SG_OFFSET_MASK);
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if (caam_dpaa2) {
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dma_to_qm_sg_one((struct dpaa2_sg_entry *)sec4_sg_ptr, dma, len,
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offset);
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} else {
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sec4_sg_ptr->ptr = cpu_to_caam_dma64(dma);
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sec4_sg_ptr->len = cpu_to_caam32(len);
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sec4_sg_ptr->bpid_offset = cpu_to_caam32(offset &
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SEC4_SG_OFFSET_MASK);
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}
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#ifdef DEBUG
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print_hex_dump(KERN_ERR, "sec4_sg_ptr@: ",
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DUMP_PREFIX_ADDRESS, 16, 4, sec4_sg_ptr,
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@ -47,6 +59,14 @@ sg_to_sec4_sg(struct scatterlist *sg, int sg_count,
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return sec4_sg_ptr - 1;
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}
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static inline void sg_to_sec4_set_last(struct sec4_sg_entry *sec4_sg_ptr)
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{
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if (caam_dpaa2)
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dpaa2_sg_set_final((struct dpaa2_sg_entry *)sec4_sg_ptr, true);
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else
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sec4_sg_ptr->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);
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}
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/*
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* convert scatterlist to h/w link table format
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* scatterlist must have been previously dma mapped
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@ -56,5 +76,7 @@ static inline void sg_to_sec4_sg_last(struct scatterlist *sg, int sg_count,
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u16 offset)
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{
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sec4_sg_ptr = sg_to_sec4_sg(sg, sg_count, sec4_sg_ptr, offset);
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sec4_sg_ptr->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);
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sg_to_sec4_set_last(sec4_sg_ptr);
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}
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#endif /* _SG_SW_SEC4_H_ */
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