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drm/i915/psr: Panel replay uses SRD_STATUS to track it's status

Browse source 
DP Panel replay uses SRD_STATUS to track it's status despite selective
update mode.

Bspec: 53370, 68920

v4:
  - use PSR2_STATUS for eDP Panel Replay
  - handle intel_psr_wait_exit_locked as well
v3:
  - do not use PSR2_STATUS for PSR1
v2:
  - use intel_dp_is_edp to differentiate
  - modify debugfs status as well

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-9-jouni.hogander@intel.com
This commit is contained in:
Jouni Högander 2024-05-10 12:38:19 +03:00
parent d210d8c0df
commit 29fb595d48
1 changed files with 16 additions and 4 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

20
drivers/gpu/drm/i915/display/intel_psr.c
View file

@ -2111,7 +2111,8 @@ static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
i915_reg_t psr_status; i915_reg_t psr_status;
u32 psr_status_mask; u32 psr_status_mask;
if (intel_dp->psr.sel_update_enabled) { if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||
intel_dp->psr.panel_replay_enabled)) {
psr_status = EDP_PSR2_STATUS(dev_priv, cpu_transcoder); psr_status = EDP_PSR2_STATUS(dev_priv, cpu_transcoder);
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
} else { } else {
@ -2849,6 +2850,13 @@ static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
EDP_PSR_STATUS_STATE_MASK, 50); EDP_PSR_STATUS_STATE_MASK, 50);
} }
static int _panel_replay_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
{
return intel_dp_is_edp(intel_dp) ?
_psr2_ready_for_pipe_update_locked(intel_dp) :
_psr1_ready_for_pipe_update_locked(intel_dp);
}
/** /**
* intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update
* @new_crtc_state: new CRTC state * @new_crtc_state: new CRTC state
@ -2874,7 +2882,9 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat
if (!intel_dp->psr.enabled) if (!intel_dp->psr.enabled)
continue; continue;
if (intel_dp->psr.sel_update_enabled) if (intel_dp->psr.panel_replay_enabled)
ret = _panel_replay_ready_for_pipe_update_locked(intel_dp);
else if (intel_dp->psr.sel_update_enabled)
ret = _psr2_ready_for_pipe_update_locked(intel_dp); ret = _psr2_ready_for_pipe_update_locked(intel_dp);
else else
ret = _psr1_ready_for_pipe_update_locked(intel_dp); ret = _psr1_ready_for_pipe_update_locked(intel_dp);
@ -2895,7 +2905,8 @@ static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
if (!intel_dp->psr.enabled) if (!intel_dp->psr.enabled)
return false; return false;
if (intel_dp->psr.sel_update_enabled) { if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||
intel_dp->psr.panel_replay_enabled)) {
reg = EDP_PSR2_STATUS(dev_priv, cpu_transcoder); reg = EDP_PSR2_STATUS(dev_priv, cpu_transcoder);
mask = EDP_PSR2_STATUS_STATE_MASK; mask = EDP_PSR2_STATUS_STATE_MASK;
} else { } else {
@ -3517,7 +3528,8 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
const char *status = "unknown"; const char *status = "unknown";
u32 val, status_val; u32 val, status_val;
if (intel_dp->psr.sel_update_enabled) { if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||
intel_dp->psr.panel_replay_enabled)) {
static const char * const live_status[] = { static const char * const live_status[] = {
"IDLE", "IDLE",
"CAPTURE", "CAPTURE",