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PCI: tegra: Convert to MSI domains
In anticipation of the removal of the msi_controller structure, convert the Tegra host controller driver to MSI domains. We end-up with the usual two domain structure, the top one being a generic PCI/MSI domain, the bottom one being Tegra-specific and handling the actual HW interrupt allocation. While at it, convert the normal interrupt handler to a chained handler, handle the controller's MSI IRQ edge triggered, support multiple MSIs per device and use the AFI_MSI_EN_VEC* registers to provide MSI masking. [treding@nvidia.com: fix, clean up and address TODOs from Marc's draft] Link: https://lore.kernel.org/r/20210330151145.997953-2-maz@kernel.org Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Marc Zyngier
Lorenzo Pieralisi
parent
a38fd87484
commit
2c99e55f79
2 changed files with 198 additions and 166 deletions
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@ -41,7 +41,6 @@ config PCI_TEGRA
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bool "NVIDIA Tegra PCIe controller"
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depends on ARCH_TEGRA || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCI_MSI_ARCH_FALLBACKS
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help
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Say Y here if you want support for the PCIe host controller found
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on NVIDIA Tegra SoCs.
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@ -21,6 +21,7 @@
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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@ -78,23 +79,8 @@
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#define AFI_MSI_FPCI_BAR_ST 0x64
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#define AFI_MSI_AXI_BAR_ST 0x68
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#define AFI_MSI_VEC0 0x6c
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#define AFI_MSI_VEC1 0x70
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#define AFI_MSI_VEC2 0x74
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#define AFI_MSI_VEC3 0x78
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#define AFI_MSI_VEC4 0x7c
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#define AFI_MSI_VEC5 0x80
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#define AFI_MSI_VEC6 0x84
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#define AFI_MSI_VEC7 0x88
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#define AFI_MSI_EN_VEC0 0x8c
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#define AFI_MSI_EN_VEC1 0x90
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#define AFI_MSI_EN_VEC2 0x94
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#define AFI_MSI_EN_VEC3 0x98
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#define AFI_MSI_EN_VEC4 0x9c
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#define AFI_MSI_EN_VEC5 0xa0
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#define AFI_MSI_EN_VEC6 0xa4
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#define AFI_MSI_EN_VEC7 0xa8
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#define AFI_MSI_VEC(x) (0x6c + ((x) * 4))
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#define AFI_MSI_EN_VEC(x) (0x8c + ((x) * 4))
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#define AFI_CONFIGURATION 0xac
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#define AFI_CONFIGURATION_EN_FPCI (1 << 0)
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@ -280,10 +266,10 @@
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#define LINK_RETRAIN_TIMEOUT 100000 /* in usec */
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struct tegra_msi {
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struct msi_controller chip;
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DECLARE_BITMAP(used, INT_PCI_MSI_NR);
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struct irq_domain *domain;
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struct mutex lock;
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struct mutex map_lock;
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spinlock_t mask_lock;
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void *virt;
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dma_addr_t phys;
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int irq;
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@ -333,11 +319,6 @@ struct tegra_pcie_soc {
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} ectl;
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};
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static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
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{
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return container_of(chip, struct tegra_msi, chip);
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}
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struct tegra_pcie {
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struct device *dev;
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@ -372,6 +353,11 @@ struct tegra_pcie {
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struct dentry *debugfs;
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};
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static inline struct tegra_pcie *msi_to_pcie(struct tegra_msi *msi)
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{
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return container_of(msi, struct tegra_pcie, msi);
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}
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struct tegra_pcie_port {
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struct tegra_pcie *pcie;
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struct device_node *np;
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@ -1432,7 +1418,6 @@ static void tegra_pcie_phys_put(struct tegra_pcie *pcie)
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}
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}
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static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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@ -1509,6 +1494,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
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phys_put:
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if (soc->program_uphy)
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tegra_pcie_phys_put(pcie);
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return err;
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}
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@ -1551,161 +1537,227 @@ static void tegra_pcie_pme_turnoff(struct tegra_pcie_port *port)
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afi_writel(pcie, val, AFI_PCIE_PME);
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}
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static int tegra_msi_alloc(struct tegra_msi *chip)
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static void tegra_pcie_msi_irq(struct irq_desc *desc)
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{
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int msi;
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mutex_lock(&chip->lock);
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msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
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if (msi < INT_PCI_MSI_NR)
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set_bit(msi, chip->used);
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else
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msi = -ENOSPC;
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mutex_unlock(&chip->lock);
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return msi;
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}
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static void tegra_msi_free(struct tegra_msi *chip, unsigned long irq)
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{
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struct device *dev = chip->chip.dev;
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mutex_lock(&chip->lock);
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if (!test_bit(irq, chip->used))
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dev_err(dev, "trying to free unused MSI#%lu\n", irq);
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else
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clear_bit(irq, chip->used);
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mutex_unlock(&chip->lock);
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}
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static irqreturn_t tegra_pcie_msi_irq(int irq, void *data)
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{
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struct tegra_pcie *pcie = data;
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struct device *dev = pcie->dev;
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struct tegra_pcie *pcie = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct tegra_msi *msi = &pcie->msi;
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unsigned int i, processed = 0;
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struct device *dev = pcie->dev;
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unsigned int i;
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chained_irq_enter(chip, desc);
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for (i = 0; i < 8; i++) {
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unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
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unsigned long reg = afi_readl(pcie, AFI_MSI_VEC(i));
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while (reg) {
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unsigned int offset = find_first_bit(®, 32);
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unsigned int index = i * 32 + offset;
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unsigned int irq;
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/* clear the interrupt */
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afi_writel(pcie, 1 << offset, AFI_MSI_VEC0 + i * 4);
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irq = irq_find_mapping(msi->domain, index);
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irq = irq_find_mapping(msi->domain->parent, index);
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if (irq) {
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if (test_bit(index, msi->used))
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generic_handle_irq(irq);
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else
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dev_info(dev, "unhandled MSI\n");
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} else {
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/*
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* that's weird who triggered this?
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* just clear it
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*/
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dev_info(dev, "unexpected MSI\n");
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afi_writel(pcie, BIT(index % 32), AFI_MSI_VEC(index));
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}
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/* see if there's any more pending in this vector */
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reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
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processed++;
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reg = afi_readl(pcie, AFI_MSI_VEC(i));
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}
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}
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return processed > 0 ? IRQ_HANDLED : IRQ_NONE;
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chained_irq_exit(chip, desc);
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}
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static int tegra_msi_setup_irq(struct msi_controller *chip,
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struct pci_dev *pdev, struct msi_desc *desc)
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static void tegra_msi_top_irq_ack(struct irq_data *d)
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{
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struct tegra_msi *msi = to_tegra_msi(chip);
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struct msi_msg msg;
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unsigned int irq;
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int hwirq;
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hwirq = tegra_msi_alloc(msi);
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if (hwirq < 0)
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return hwirq;
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irq = irq_create_mapping(msi->domain, hwirq);
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if (!irq) {
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tegra_msi_free(msi, hwirq);
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return -EINVAL;
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}
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irq_set_msi_desc(irq, desc);
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msg.address_lo = lower_32_bits(msi->phys);
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msg.address_hi = upper_32_bits(msi->phys);
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msg.data = hwirq;
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pci_write_msi_msg(irq, &msg);
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return 0;
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irq_chip_ack_parent(d);
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}
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static void tegra_msi_teardown_irq(struct msi_controller *chip,
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unsigned int irq)
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static void tegra_msi_top_irq_mask(struct irq_data *d)
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{
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struct tegra_msi *msi = to_tegra_msi(chip);
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struct irq_data *d = irq_get_irq_data(irq);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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irq_dispose_mapping(irq);
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tegra_msi_free(msi, hwirq);
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pci_msi_mask_irq(d);
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irq_chip_mask_parent(d);
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}
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static struct irq_chip tegra_msi_irq_chip = {
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static void tegra_msi_top_irq_unmask(struct irq_data *d)
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{
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pci_msi_unmask_irq(d);
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irq_chip_unmask_parent(d);
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}
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static struct irq_chip tegra_msi_top_chip = {
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.name = "Tegra PCIe MSI",
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.irq_enable = pci_msi_unmask_irq,
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.irq_disable = pci_msi_mask_irq,
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.irq_mask = pci_msi_mask_irq,
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.irq_unmask = pci_msi_unmask_irq,
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.irq_ack = tegra_msi_top_irq_ack,
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.irq_mask = tegra_msi_top_irq_mask,
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.irq_unmask = tegra_msi_top_irq_unmask,
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};
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static int tegra_msi_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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static void tegra_msi_irq_ack(struct irq_data *d)
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{
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irq_set_chip_and_handler(irq, &tegra_msi_irq_chip, handle_simple_irq);
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irq_set_chip_data(irq, domain->host_data);
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struct tegra_msi *msi = irq_data_get_irq_chip_data(d);
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struct tegra_pcie *pcie = msi_to_pcie(msi);
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unsigned int index = d->hwirq / 32;
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/* clear the interrupt */
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afi_writel(pcie, BIT(d->hwirq % 32), AFI_MSI_VEC(index));
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}
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static void tegra_msi_irq_mask(struct irq_data *d)
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{
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struct tegra_msi *msi = irq_data_get_irq_chip_data(d);
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struct tegra_pcie *pcie = msi_to_pcie(msi);
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unsigned int index = d->hwirq / 32;
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unsigned long flags;
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u32 value;
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spin_lock_irqsave(&msi->mask_lock, flags);
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value = afi_readl(pcie, AFI_MSI_EN_VEC(index));
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value &= ~BIT(d->hwirq % 32);
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afi_writel(pcie, value, AFI_MSI_EN_VEC(index));
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spin_unlock_irqrestore(&msi->mask_lock, flags);
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}
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static void tegra_msi_irq_unmask(struct irq_data *d)
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{
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struct tegra_msi *msi = irq_data_get_irq_chip_data(d);
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struct tegra_pcie *pcie = msi_to_pcie(msi);
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unsigned int index = d->hwirq / 32;
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unsigned long flags;
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u32 value;
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spin_lock_irqsave(&msi->mask_lock, flags);
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value = afi_readl(pcie, AFI_MSI_EN_VEC(index));
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value |= BIT(d->hwirq % 32);
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afi_writel(pcie, value, AFI_MSI_EN_VEC(index));
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spin_unlock_irqrestore(&msi->mask_lock, flags);
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}
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static int tegra_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force)
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{
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return -EINVAL;
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}
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static void tegra_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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{
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struct tegra_msi *msi = irq_data_get_irq_chip_data(data);
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msg->address_lo = lower_32_bits(msi->phys);
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msg->address_hi = upper_32_bits(msi->phys);
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msg->data = data->hwirq;
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}
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static struct irq_chip tegra_msi_bottom_chip = {
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.name = "Tegra MSI",
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.irq_ack = tegra_msi_irq_ack,
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.irq_mask = tegra_msi_irq_mask,
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.irq_unmask = tegra_msi_irq_unmask,
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.irq_set_affinity = tegra_msi_set_affinity,
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.irq_compose_msi_msg = tegra_compose_msi_msg,
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};
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static int tegra_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *args)
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{
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struct tegra_msi *msi = domain->host_data;
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unsigned int i;
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int hwirq;
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mutex_lock(&msi->map_lock);
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hwirq = bitmap_find_free_region(msi->used, INT_PCI_MSI_NR, order_base_2(nr_irqs));
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mutex_unlock(&msi->map_lock);
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if (hwirq < 0)
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return -ENOSPC;
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for (i = 0; i < nr_irqs; i++)
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irq_domain_set_info(domain, virq + i, hwirq + i,
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&tegra_msi_bottom_chip, domain->host_data,
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handle_edge_irq, NULL, NULL);
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tegra_cpuidle_pcie_irqs_in_use();
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return 0;
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}
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static const struct irq_domain_ops msi_domain_ops = {
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.map = tegra_msi_map,
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static void tegra_msi_domain_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs)
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{
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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struct tegra_msi *msi = domain->host_data;
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mutex_lock(&msi->map_lock);
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bitmap_release_region(msi->used, d->hwirq, order_base_2(nr_irqs));
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mutex_unlock(&msi->map_lock);
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}
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static const struct irq_domain_ops tegra_msi_domain_ops = {
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.alloc = tegra_msi_domain_alloc,
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.free = tegra_msi_domain_free,
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};
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static struct msi_domain_info tegra_msi_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_PCI_MSIX),
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.chip = &tegra_msi_top_chip,
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};
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static int tegra_allocate_domains(struct tegra_msi *msi)
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{
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struct tegra_pcie *pcie = msi_to_pcie(msi);
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struct fwnode_handle *fwnode = dev_fwnode(pcie->dev);
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struct irq_domain *parent;
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parent = irq_domain_create_linear(fwnode, INT_PCI_MSI_NR,
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&tegra_msi_domain_ops, msi);
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if (!parent) {
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dev_err(pcie->dev, "failed to create IRQ domain\n");
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return -ENOMEM;
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}
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irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS);
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msi->domain = pci_msi_create_irq_domain(fwnode, &tegra_msi_info, parent);
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if (!msi->domain) {
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dev_err(pcie->dev, "failed to create MSI domain\n");
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irq_domain_remove(parent);
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return -ENOMEM;
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}
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return 0;
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}
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static void tegra_free_domains(struct tegra_msi *msi)
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{
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struct irq_domain *parent = msi->domain->parent;
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irq_domain_remove(msi->domain);
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irq_domain_remove(parent);
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}
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static int tegra_pcie_msi_setup(struct tegra_pcie *pcie)
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{
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struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
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struct platform_device *pdev = to_platform_device(pcie->dev);
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struct tegra_msi *msi = &pcie->msi;
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struct device *dev = pcie->dev;
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int err;
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mutex_init(&msi->lock);
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mutex_init(&msi->map_lock);
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spin_lock_init(&msi->mask_lock);
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msi->chip.dev = dev;
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msi->chip.setup_irq = tegra_msi_setup_irq;
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msi->chip.teardown_irq = tegra_msi_teardown_irq;
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msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR,
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&msi_domain_ops, &msi->chip);
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if (!msi->domain) {
|
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dev_err(dev, "failed to create IRQ domain\n");
|
||||
return -ENOMEM;
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
||||
err = tegra_allocate_domains(msi);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
err = platform_get_irq_byname(pdev, "msi");
|
||||
|
|
@ -1714,12 +1766,7 @@ static int tegra_pcie_msi_setup(struct tegra_pcie *pcie)
|
|||
|
||||
msi->irq = err;
|
||||
|
||||
err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD,
|
||||
tegra_msi_irq_chip.name, pcie);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "failed to request IRQ: %d\n", err);
|
||||
goto free_irq_domain;
|
||||
}
|
||||
irq_set_chained_handler_and_data(msi->irq, tegra_pcie_msi_irq, pcie);
|
||||
|
||||
/* Though the PCIe controller can address >32-bit address space, to
|
||||
* facilitate endpoints that support only 32-bit MSI target address,
|
||||
|
|
@ -1740,14 +1787,14 @@ static int tegra_pcie_msi_setup(struct tegra_pcie *pcie)
|
|||
goto free_irq;
|
||||
}
|
||||
|
||||
host->msi = &msi->chip;
|
||||
|
||||
return 0;
|
||||
|
||||
free_irq:
|
||||
free_irq(msi->irq, pcie);
|
||||
irq_set_chained_handler_and_data(msi->irq, NULL, NULL);
|
||||
free_irq_domain:
|
||||
irq_domain_remove(msi->domain);
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI))
|
||||
tegra_free_domains(msi);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
|
|
@ -1755,22 +1802,18 @@ static void tegra_pcie_enable_msi(struct tegra_pcie *pcie)
|
|||
{
|
||||
const struct tegra_pcie_soc *soc = pcie->soc;
|
||||
struct tegra_msi *msi = &pcie->msi;
|
||||
u32 reg;
|
||||
u32 reg, msi_state[INT_PCI_MSI_NR / 32];
|
||||
int i;
|
||||
|
||||
afi_writel(pcie, msi->phys >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);
|
||||
afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST);
|
||||
/* this register is in 4K increments */
|
||||
afi_writel(pcie, 1, AFI_MSI_BAR_SZ);
|
||||
|
||||
/* enable all MSI vectors */
|
||||
afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC0);
|
||||
afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC1);
|
||||
afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC2);
|
||||
afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC3);
|
||||
afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC4);
|
||||
afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC5);
|
||||
afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC6);
|
||||
afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC7);
|
||||
/* Restore the MSI allocation state */
|
||||
bitmap_to_arr32(msi_state, msi->used, INT_PCI_MSI_NR);
|
||||
for (i = 0; i < ARRAY_SIZE(msi_state); i++)
|
||||
afi_writel(pcie, msi_state[i], AFI_MSI_EN_VEC(i));
|
||||
|
||||
/* and unmask the MSI interrupt */
|
||||
reg = afi_readl(pcie, AFI_INTR_MASK);
|
||||
|
|
@ -1786,16 +1829,16 @@ static void tegra_pcie_msi_teardown(struct tegra_pcie *pcie)
|
|||
dma_free_attrs(pcie->dev, PAGE_SIZE, msi->virt, msi->phys,
|
||||
DMA_ATTR_NO_KERNEL_MAPPING);
|
||||
|
||||
if (msi->irq > 0)
|
||||
free_irq(msi->irq, pcie);
|
||||
|
||||
for (i = 0; i < INT_PCI_MSI_NR; i++) {
|
||||
irq = irq_find_mapping(msi->domain, i);
|
||||
if (irq > 0)
|
||||
irq_dispose_mapping(irq);
|
||||
irq_domain_free_irqs(irq, 1);
|
||||
}
|
||||
|
||||
irq_domain_remove(msi->domain);
|
||||
irq_set_chained_handler_and_data(msi->irq, NULL, NULL);
|
||||
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI))
|
||||
tegra_free_domains(msi);
|
||||
}
|
||||
|
||||
static int tegra_pcie_disable_msi(struct tegra_pcie *pcie)
|
||||
|
|
@ -1807,16 +1850,6 @@ static int tegra_pcie_disable_msi(struct tegra_pcie *pcie)
|
|||
value &= ~AFI_INTR_MASK_MSI_MASK;
|
||||
afi_writel(pcie, value, AFI_INTR_MASK);
|
||||
|
||||
/* disable all MSI vectors */
|
||||
afi_writel(pcie, 0, AFI_MSI_EN_VEC0);
|
||||
afi_writel(pcie, 0, AFI_MSI_EN_VEC1);
|
||||
afi_writel(pcie, 0, AFI_MSI_EN_VEC2);
|
||||
afi_writel(pcie, 0, AFI_MSI_EN_VEC3);
|
||||
afi_writel(pcie, 0, AFI_MSI_EN_VEC4);
|
||||
afi_writel(pcie, 0, AFI_MSI_EN_VEC5);
|
||||
afi_writel(pcie, 0, AFI_MSI_EN_VEC6);
|
||||
afi_writel(pcie, 0, AFI_MSI_EN_VEC7);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue