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PCI: xilinx-nwl: Modify ECAM size to enable support for 256 buses

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The PCIe Root Port controller expects ECAM size to be set through software.

As such, update the value of the NWL_ECAM_VALUE_DEFAULT macro to 16 to
allow the controller to address the 256 MB ECAM region and, as such,
enable support for detecting up to 256 buses.

[kwilczynski: commit log]
Link: https://patchwork.kernel.org/project/linux-pci/patch/20231016051102.1180432-5-thippeswamy.havalige@amd.com/
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
This commit is contained in:
Thippeswamy Havalige 2023-10-16 10:41:02 +05:30 committed by Krzysztof Wilczyński
parent 177692115f
commit 2fccd11518
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1 changed files with 1 additions and 1 deletions
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2
drivers/pci/controller/pcie-xilinx-nwl.c
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@ -126,7 +126,7 @@
#define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_CR_ENABLE BIT(0)
#define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_LOC GENMASK(20, 16)
#define E_ECAM_SIZE_SHIFT 16 #define E_ECAM_SIZE_SHIFT 16
#define NWL_ECAM_MAX_SIZE 12 #define NWL_ECAM_MAX_SIZE 16
#define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_DMA_REG_BAR GENMASK(2, 0)
#define CFG_PCIE_CACHE GENMASK(7, 0) #define CFG_PCIE_CACHE GENMASK(7, 0)