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bpf: Add x86-64 JIT support for PROBE_MEM32 pseudo instructions.
Add support for [LDX | STX | ST], PROBE_MEM32, [B | H | W | DW] instructions. They are similar to PROBE_MEM instructions with the following differences: - PROBE_MEM has to check that the address is in the kernel range with src_reg + insn->off >= TASK_SIZE_MAX + PAGE_SIZE check - PROBE_MEM doesn't support store - PROBE_MEM32 relies on the verifier to clear upper 32-bit in the register - PROBE_MEM32 adds 64-bit kern_vm_start address (which is stored in %r12 in the prologue) Due to bpf_arena constructions such %r12 + %reg + off16 access is guaranteed to be within arena virtual range, so no address check at run-time. - PROBE_MEM32 allows STX and ST. If they fault the store is a nop. When LDX faults the destination register is zeroed. Signed-off-by: Alexei Starovoitov <ast@kernel.org> Signed-off-by: Andrii Nakryiko <andrii@kernel.org> Acked-by: Kumar Kartikeya Dwivedi <memxor@gmail.com> Link: https://lore.kernel.org/bpf/20240308010812.89848-4-alexei.starovoitov@gmail.com
This commit is contained in:
Alexei Starovoitov
Andrii Nakryiko
parent
667a86ad9b
commit
2fe99eb0cc
3 changed files with 194 additions and 1 deletions
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@ -113,6 +113,7 @@ static int bpf_size_to_x86_bytes(int bpf_size)
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/* Pick a register outside of BPF range for JIT internal work */
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#define AUX_REG (MAX_BPF_JIT_REG + 1)
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#define X86_REG_R9 (MAX_BPF_JIT_REG + 2)
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#define X86_REG_R12 (MAX_BPF_JIT_REG + 3)
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/*
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* The following table maps BPF registers to x86-64 registers.
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@ -139,6 +140,7 @@ static const int reg2hex[] = {
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[BPF_REG_AX] = 2, /* R10 temp register */
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[AUX_REG] = 3, /* R11 temp register */
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[X86_REG_R9] = 1, /* R9 register, 6th function argument */
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[X86_REG_R12] = 4, /* R12 callee saved */
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};
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static const int reg2pt_regs[] = {
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@ -167,6 +169,7 @@ static bool is_ereg(u32 reg)
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BIT(BPF_REG_8) |
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BIT(BPF_REG_9) |
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BIT(X86_REG_R9) |
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BIT(X86_REG_R12) |
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BIT(BPF_REG_AX));
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}
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@ -205,6 +208,17 @@ static u8 add_2mod(u8 byte, u32 r1, u32 r2)
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return byte;
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}
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static u8 add_3mod(u8 byte, u32 r1, u32 r2, u32 index)
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{
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if (is_ereg(r1))
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byte |= 1;
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if (is_ereg(index))
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byte |= 2;
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if (is_ereg(r2))
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byte |= 4;
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return byte;
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}
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/* Encode 'dst_reg' register into x86-64 opcode 'byte' */
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static u8 add_1reg(u8 byte, u32 dst_reg)
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{
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@ -645,6 +659,8 @@ static void emit_bpf_tail_call_indirect(struct bpf_prog *bpf_prog,
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pop_r12(&prog);
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} else {
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pop_callee_regs(&prog, callee_regs_used);
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if (bpf_arena_get_kern_vm_start(bpf_prog->aux->arena))
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pop_r12(&prog);
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}
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EMIT1(0x58); /* pop rax */
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@ -704,6 +720,8 @@ static void emit_bpf_tail_call_direct(struct bpf_prog *bpf_prog,
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pop_r12(&prog);
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} else {
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pop_callee_regs(&prog, callee_regs_used);
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if (bpf_arena_get_kern_vm_start(bpf_prog->aux->arena))
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pop_r12(&prog);
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}
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EMIT1(0x58); /* pop rax */
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@ -887,6 +905,18 @@ static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off)
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*pprog = prog;
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}
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static void emit_insn_suffix_SIB(u8 **pprog, u32 ptr_reg, u32 val_reg, u32 index_reg, int off)
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{
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u8 *prog = *pprog;
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if (is_imm8(off)) {
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EMIT3(add_2reg(0x44, BPF_REG_0, val_reg), add_2reg(0, ptr_reg, index_reg) /* SIB */, off);
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} else {
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EMIT2_off32(add_2reg(0x84, BPF_REG_0, val_reg), add_2reg(0, ptr_reg, index_reg) /* SIB */, off);
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}
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*pprog = prog;
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}
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/*
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* Emit a REX byte if it will be necessary to address these registers
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*/
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@ -968,6 +998,37 @@ static void emit_ldsx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
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*pprog = prog;
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}
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static void emit_ldx_index(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, u32 index_reg, int off)
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{
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u8 *prog = *pprog;
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switch (size) {
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case BPF_B:
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/* movzx rax, byte ptr [rax + r12 + off] */
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EMIT3(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x0F, 0xB6);
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break;
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case BPF_H:
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/* movzx rax, word ptr [rax + r12 + off] */
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EMIT3(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x0F, 0xB7);
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break;
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case BPF_W:
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/* mov eax, dword ptr [rax + r12 + off] */
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EMIT2(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x8B);
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break;
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case BPF_DW:
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/* mov rax, qword ptr [rax + r12 + off] */
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EMIT2(add_3mod(0x48, src_reg, dst_reg, index_reg), 0x8B);
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break;
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}
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emit_insn_suffix_SIB(&prog, src_reg, dst_reg, index_reg, off);
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*pprog = prog;
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}
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static void emit_ldx_r12(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
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{
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emit_ldx_index(pprog, size, dst_reg, src_reg, X86_REG_R12, off);
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}
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/* STX: *(u8*)(dst_reg + off) = src_reg */
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static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
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{
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@ -1002,6 +1063,71 @@ static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
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*pprog = prog;
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}
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/* STX: *(u8*)(dst_reg + index_reg + off) = src_reg */
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static void emit_stx_index(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, u32 index_reg, int off)
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{
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u8 *prog = *pprog;
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switch (size) {
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case BPF_B:
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/* mov byte ptr [rax + r12 + off], al */
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EMIT2(add_3mod(0x40, dst_reg, src_reg, index_reg), 0x88);
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break;
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case BPF_H:
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/* mov word ptr [rax + r12 + off], ax */
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EMIT3(0x66, add_3mod(0x40, dst_reg, src_reg, index_reg), 0x89);
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break;
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case BPF_W:
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/* mov dword ptr [rax + r12 + 1], eax */
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EMIT2(add_3mod(0x40, dst_reg, src_reg, index_reg), 0x89);
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break;
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case BPF_DW:
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/* mov qword ptr [rax + r12 + 1], rax */
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EMIT2(add_3mod(0x48, dst_reg, src_reg, index_reg), 0x89);
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break;
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}
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emit_insn_suffix_SIB(&prog, dst_reg, src_reg, index_reg, off);
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*pprog = prog;
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}
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static void emit_stx_r12(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
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{
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emit_stx_index(pprog, size, dst_reg, src_reg, X86_REG_R12, off);
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}
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/* ST: *(u8*)(dst_reg + index_reg + off) = imm32 */
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static void emit_st_index(u8 **pprog, u32 size, u32 dst_reg, u32 index_reg, int off, int imm)
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{
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u8 *prog = *pprog;
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switch (size) {
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case BPF_B:
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/* mov byte ptr [rax + r12 + off], imm8 */
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EMIT2(add_3mod(0x40, dst_reg, 0, index_reg), 0xC6);
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break;
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case BPF_H:
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/* mov word ptr [rax + r12 + off], imm16 */
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EMIT3(0x66, add_3mod(0x40, dst_reg, 0, index_reg), 0xC7);
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break;
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case BPF_W:
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/* mov dword ptr [rax + r12 + 1], imm32 */
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EMIT2(add_3mod(0x40, dst_reg, 0, index_reg), 0xC7);
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break;
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case BPF_DW:
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/* mov qword ptr [rax + r12 + 1], imm32 */
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EMIT2(add_3mod(0x48, dst_reg, 0, index_reg), 0xC7);
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break;
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}
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emit_insn_suffix_SIB(&prog, dst_reg, 0, index_reg, off);
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EMIT(imm, bpf_size_to_x86_bytes(size));
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*pprog = prog;
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}
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static void emit_st_r12(u8 **pprog, u32 size, u32 dst_reg, int off, int imm)
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{
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emit_st_index(pprog, size, dst_reg, X86_REG_R12, off, imm);
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}
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static int emit_atomic(u8 **pprog, u8 atomic_op,
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u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size)
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{
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@ -1043,12 +1169,15 @@ static int emit_atomic(u8 **pprog, u8 atomic_op,
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return 0;
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}
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#define DONT_CLEAR 1
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bool ex_handler_bpf(const struct exception_table_entry *x, struct pt_regs *regs)
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{
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u32 reg = x->fixup >> 8;
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/* jump over faulting load and clear dest register */
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*(unsigned long *)((void *)regs + reg) = 0;
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if (reg != DONT_CLEAR)
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*(unsigned long *)((void *)regs + reg) = 0;
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regs->ip += x->fixup & 0xff;
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return true;
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}
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@ -1147,11 +1276,14 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image
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bool tail_call_seen = false;
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bool seen_exit = false;
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u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY];
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u64 arena_vm_start;
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int i, excnt = 0;
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int ilen, proglen = 0;
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u8 *prog = temp;
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int err;
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arena_vm_start = bpf_arena_get_kern_vm_start(bpf_prog->aux->arena);
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detect_reg_usage(insn, insn_cnt, callee_regs_used,
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&tail_call_seen);
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@ -1172,8 +1304,13 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image
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push_r12(&prog);
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push_callee_regs(&prog, all_callee_regs_used);
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} else {
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if (arena_vm_start)
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push_r12(&prog);
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push_callee_regs(&prog, callee_regs_used);
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}
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if (arena_vm_start)
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emit_mov_imm64(&prog, X86_REG_R12,
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arena_vm_start >> 32, (u32) arena_vm_start);
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ilen = prog - temp;
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if (rw_image)
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@ -1564,6 +1701,56 @@ st: if (is_imm8(insn->off))
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emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
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break;
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case BPF_ST | BPF_PROBE_MEM32 | BPF_B:
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case BPF_ST | BPF_PROBE_MEM32 | BPF_H:
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case BPF_ST | BPF_PROBE_MEM32 | BPF_W:
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case BPF_ST | BPF_PROBE_MEM32 | BPF_DW:
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start_of_ldx = prog;
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emit_st_r12(&prog, BPF_SIZE(insn->code), dst_reg, insn->off, insn->imm);
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goto populate_extable;
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/* LDX: dst_reg = *(u8*)(src_reg + r12 + off) */
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case BPF_LDX | BPF_PROBE_MEM32 | BPF_B:
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case BPF_LDX | BPF_PROBE_MEM32 | BPF_H:
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case BPF_LDX | BPF_PROBE_MEM32 | BPF_W:
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case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW:
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case BPF_STX | BPF_PROBE_MEM32 | BPF_B:
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case BPF_STX | BPF_PROBE_MEM32 | BPF_H:
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case BPF_STX | BPF_PROBE_MEM32 | BPF_W:
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case BPF_STX | BPF_PROBE_MEM32 | BPF_DW:
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start_of_ldx = prog;
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if (BPF_CLASS(insn->code) == BPF_LDX)
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emit_ldx_r12(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
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else
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emit_stx_r12(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
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populate_extable:
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{
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struct exception_table_entry *ex;
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u8 *_insn = image + proglen + (start_of_ldx - temp);
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s64 delta;
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if (!bpf_prog->aux->extable)
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break;
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if (excnt >= bpf_prog->aux->num_exentries) {
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pr_err("mem32 extable bug\n");
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return -EFAULT;
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}
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ex = &bpf_prog->aux->extable[excnt++];
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delta = _insn - (u8 *)&ex->insn;
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/* switch ex to rw buffer for writes */
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ex = (void *)rw_image + ((void *)ex - (void *)image);
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ex->insn = delta;
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ex->data = EX_TYPE_BPF;
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ex->fixup = (prog - start_of_ldx) |
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((BPF_CLASS(insn->code) == BPF_LDX ? reg2pt_regs[dst_reg] : DONT_CLEAR) << 8);
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}
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break;
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/* LDX: dst_reg = *(u8*)(src_reg + off) */
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case BPF_LDX | BPF_MEM | BPF_B:
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case BPF_LDX | BPF_PROBE_MEM | BPF_B:
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@ -2036,6 +2223,8 @@ st: if (is_imm8(insn->off))
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pop_r12(&prog);
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} else {
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pop_callee_regs(&prog, callee_regs_used);
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if (arena_vm_start)
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pop_r12(&prog);
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}
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EMIT1(0xC9); /* leave */
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emit_return(&prog, image + addrs[i - 1] + (prog - temp));
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@ -1458,6 +1458,7 @@ struct bpf_prog_aux {
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bool xdp_has_frags;
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bool exception_cb;
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bool exception_boundary;
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struct bpf_arena *arena;
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/* BTF_KIND_FUNC_PROTO for valid attach_btf_id */
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const struct btf_type *attach_func_proto;
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/* function name for valid attach_btf_id */
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@ -72,6 +72,9 @@ struct ctl_table_header;
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/* unused opcode to mark special ldsx instruction. Same as BPF_IND */
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#define BPF_PROBE_MEMSX 0x40
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/* unused opcode to mark special load instruction. Same as BPF_MSH */
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#define BPF_PROBE_MEM32 0xa0
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/* unused opcode to mark call to interpreter with arguments */
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#define BPF_CALL_ARGS 0xe0
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