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clk: renesas: cpg-mssr: Add support for R-Car E3
Initial support for R-Car E3 (r8a77990), including core and module clocks. Based on the Table 8.2g of "R-Car Series, 3rd Generation User's Manual: Hardware ((Rev. 0.80, Oct 31, 2017) with Manual Errata on Feb. 28, 2018". Inspried by patches by Takeshi Kihara in the BSP. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Yoshihiro Shimoda
Geert Uytterhoeven
parent
9a31fa395c
commit
3570a2af47
6 changed files with 304 additions and 1 deletions
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@ -26,6 +26,7 @@ Required Properties:
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- "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
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- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
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- "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
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- "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3)
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- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
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- reg: Base address and length of the memory resource used by the CPG/MSSR
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@ -36,7 +37,7 @@ Required Properties:
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- clock-names: List of external parent clock names. Valid names are:
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- "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792,
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r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970,
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r8a77980, r8a77995)
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r8a77980, r8a77990, r8a77995)
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- "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
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- "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,
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r8a7794)
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@ -19,6 +19,7 @@ config CLK_RENESAS
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select CLK_R8A77965 if ARCH_R8A77965
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select CLK_R8A77970 if ARCH_R8A77970
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select CLK_R8A77980 if ARCH_R8A77980
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select CLK_R8A77990 if ARCH_R8A77990
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select CLK_R8A77995 if ARCH_R8A77995
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select CLK_SH73A0 if ARCH_SH73A0
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@ -116,6 +117,10 @@ config CLK_R8A77980
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bool "R-Car V3H clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A77990
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bool "R-Car E3 clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A77995
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bool "R-Car D3 clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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@ -18,6 +18,7 @@ obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
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obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
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289
drivers/clk/renesas/r8a77990-cpg-mssr.c
Normal file
289
drivers/clk/renesas/r8a77990-cpg-mssr.c
Normal file
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@ -0,0 +1,289 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* r8a77990 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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*
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* Based on r8a7795-cpg-mssr.c
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*
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* Copyright (C) 2015 Glider bvba
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* Copyright (C) 2015 Renesas Electronics Corp.
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*/
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/soc/renesas/rcar-rst.h>
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#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen3-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R8A77990_CLK_CPEX,
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/* External Input Clocks */
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CLK_EXTAL,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_PLL0,
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CLK_PLL1,
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CLK_PLL3,
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CLK_PLL0D4,
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CLK_PLL0D6,
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CLK_PLL0D8,
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CLK_PLL0D20,
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CLK_PLL0D24,
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CLK_PLL1D2,
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CLK_PE,
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CLK_S0,
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CLK_S1,
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CLK_S2,
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CLK_S3,
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CLK_SDSRC,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
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DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
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DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100),
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DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1),
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DEF_FIXED(".pll0d6", CLK_PLL0D6, CLK_PLL0, 6, 1),
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DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1),
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DEF_FIXED(".pll0d20", CLK_PLL0D20, CLK_PLL0, 20, 1),
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DEF_FIXED(".pll0d24", CLK_PLL0D24, CLK_PLL0, 24, 1),
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DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
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DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20, 1, 1),
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DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
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DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
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/* Core Clock Outputs */
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DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1),
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DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
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DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1),
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DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1),
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DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1),
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DEF_FIXED("s0d1", R8A77990_CLK_S0D1, CLK_S0, 1, 1),
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DEF_FIXED("s0d3", R8A77990_CLK_S0D3, CLK_S0, 3, 1),
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DEF_FIXED("s0d6", R8A77990_CLK_S0D6, CLK_S0, 6, 1),
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DEF_FIXED("s0d12", R8A77990_CLK_S0D12, CLK_S0, 12, 1),
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DEF_FIXED("s0d24", R8A77990_CLK_S0D24, CLK_S0, 24, 1),
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DEF_FIXED("s1d1", R8A77990_CLK_S1D1, CLK_S1, 1, 1),
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DEF_FIXED("s1d2", R8A77990_CLK_S1D2, CLK_S1, 2, 1),
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DEF_FIXED("s1d4", R8A77990_CLK_S1D4, CLK_S1, 4, 1),
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DEF_FIXED("s2d1", R8A77990_CLK_S2D1, CLK_S2, 1, 1),
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DEF_FIXED("s2d2", R8A77990_CLK_S2D2, CLK_S2, 2, 1),
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DEF_FIXED("s2d4", R8A77990_CLK_S2D4, CLK_S2, 4, 1),
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DEF_FIXED("s3d1", R8A77990_CLK_S3D1, CLK_S3, 1, 1),
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DEF_FIXED("s3d2", R8A77990_CLK_S3D2, CLK_S3, 2, 1),
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DEF_FIXED("s3d4", R8A77990_CLK_S3D4, CLK_S3, 4, 1),
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DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, CLK_SDSRC, 0x0074),
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DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078),
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DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c),
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DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
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DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1),
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DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
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DEF_FIXED("osc", R8A77990_CLK_OSC, CLK_EXTAL, 384, 1),
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DEF_FIXED("r", R8A77990_CLK_R, CLK_EXTAL, 1536, 1),
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DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
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DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
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DEF_GEN3_PE("s3d2c", R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
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DEF_GEN3_PE("s3d4c", R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
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DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
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DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c),
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DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014),
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};
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static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
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DEF_MOD("scif5", 202, R8A77990_CLK_S3D4C),
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DEF_MOD("scif4", 203, R8A77990_CLK_S3D4C),
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DEF_MOD("scif3", 204, R8A77990_CLK_S3D4C),
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DEF_MOD("scif1", 206, R8A77990_CLK_S3D4C),
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DEF_MOD("scif0", 207, R8A77990_CLK_S3D4C),
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DEF_MOD("msiof3", 208, R8A77990_CLK_MSO),
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DEF_MOD("msiof2", 209, R8A77990_CLK_MSO),
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DEF_MOD("msiof1", 210, R8A77990_CLK_MSO),
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DEF_MOD("msiof0", 211, R8A77990_CLK_MSO),
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DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),
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DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),
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DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1),
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DEF_MOD("cmt3", 300, R8A77990_CLK_R),
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DEF_MOD("cmt2", 301, R8A77990_CLK_R),
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DEF_MOD("cmt1", 302, R8A77990_CLK_R),
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DEF_MOD("cmt0", 303, R8A77990_CLK_R),
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DEF_MOD("scif2", 310, R8A77990_CLK_S3D4C),
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DEF_MOD("sdif3", 311, R8A77990_CLK_SD3),
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DEF_MOD("sdif1", 313, R8A77990_CLK_SD1),
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DEF_MOD("sdif0", 314, R8A77990_CLK_SD0),
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DEF_MOD("pcie0", 319, R8A77990_CLK_S3D1),
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DEF_MOD("usb3-if0", 328, R8A77990_CLK_S3D1),
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DEF_MOD("usb-dmac0", 330, R8A77990_CLK_S3D1),
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DEF_MOD("usb-dmac1", 331, R8A77990_CLK_S3D1),
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DEF_MOD("rwdt", 402, R8A77990_CLK_R),
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DEF_MOD("intc-ex", 407, R8A77990_CLK_CP),
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DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3),
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DEF_MOD("audmac0", 502, R8A77990_CLK_S3D4),
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DEF_MOD("drif7", 508, R8A77990_CLK_S3D2),
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DEF_MOD("drif6", 509, R8A77990_CLK_S3D2),
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DEF_MOD("drif5", 510, R8A77990_CLK_S3D2),
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DEF_MOD("drif4", 511, R8A77990_CLK_S3D2),
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DEF_MOD("drif3", 512, R8A77990_CLK_S3D2),
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DEF_MOD("drif2", 513, R8A77990_CLK_S3D2),
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DEF_MOD("drif1", 514, R8A77990_CLK_S3D2),
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DEF_MOD("drif0", 515, R8A77990_CLK_S3D2),
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DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C),
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DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C),
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DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C),
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DEF_MOD("hscif1", 519, R8A77990_CLK_S3D1C),
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DEF_MOD("hscif0", 520, R8A77990_CLK_S3D1C),
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DEF_MOD("thermal", 522, R8A77990_CLK_CP),
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DEF_MOD("pwm", 523, R8A77990_CLK_S3D4C),
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DEF_MOD("fcpvd1", 602, R8A77990_CLK_S1D2),
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DEF_MOD("fcpvd0", 603, R8A77990_CLK_S1D2),
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DEF_MOD("fcpvb0", 607, R8A77990_CLK_S0D1),
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DEF_MOD("fcpvi0", 611, R8A77990_CLK_S0D1),
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DEF_MOD("fcpf0", 615, R8A77990_CLK_S0D1),
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DEF_MOD("fcpcs", 619, R8A77990_CLK_S0D1),
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DEF_MOD("vspd1", 622, R8A77990_CLK_S1D2),
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DEF_MOD("vspd0", 623, R8A77990_CLK_S1D2),
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DEF_MOD("vspb", 626, R8A77990_CLK_S0D1),
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DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1),
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DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4),
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DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4),
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DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
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DEF_MOD("du1", 723, R8A77990_CLK_S2D1),
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DEF_MOD("du0", 724, R8A77990_CLK_S2D1),
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DEF_MOD("lvds", 727, R8A77990_CLK_S2D1),
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DEF_MOD("vin5", 806, R8A77990_CLK_S1D2),
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DEF_MOD("vin4", 807, R8A77990_CLK_S1D2),
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DEF_MOD("etheravb", 812, R8A77990_CLK_S3D2),
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DEF_MOD("gpio6", 906, R8A77990_CLK_S3D4),
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DEF_MOD("gpio5", 907, R8A77990_CLK_S3D4),
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DEF_MOD("gpio4", 908, R8A77990_CLK_S3D4),
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DEF_MOD("gpio3", 909, R8A77990_CLK_S3D4),
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DEF_MOD("gpio2", 910, R8A77990_CLK_S3D4),
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DEF_MOD("gpio1", 911, R8A77990_CLK_S3D4),
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DEF_MOD("gpio0", 912, R8A77990_CLK_S3D4),
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DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2),
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DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4),
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DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4),
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DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2),
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DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2),
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DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP),
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DEF_MOD("i2c4", 927, R8A77990_CLK_S3D2),
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DEF_MOD("i2c3", 928, R8A77990_CLK_S3D2),
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DEF_MOD("i2c2", 929, R8A77990_CLK_S3D2),
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DEF_MOD("i2c1", 930, R8A77990_CLK_S3D2),
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DEF_MOD("i2c0", 931, R8A77990_CLK_S3D2),
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DEF_MOD("ssi-all", 1005, R8A77990_CLK_S3D4),
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DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
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DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
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DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
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DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
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DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
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DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
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DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
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DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
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DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
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DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
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DEF_MOD("scu-all", 1017, R8A77990_CLK_S3D4),
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DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
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DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
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DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
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DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
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};
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static const unsigned int r8a77990_crit_mod_clks[] __initconst = {
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MOD_CLK_ID(408), /* INTC-AP (GIC) */
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};
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/*
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* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
|
||||
*--------------------------------------------------------------------
|
||||
* 0 48 x 1 x100/4 x100/3 x100/3
|
||||
* 1 48 x 1 x100/4 x100/3 x58/3
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 100, 3, 100, 3, },
|
||||
{ 1, 100, 3, 58, 3, },
|
||||
};
|
||||
|
||||
static int __init r8a77990_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
|
||||
u32 cpg_mode;
|
||||
int error;
|
||||
|
||||
error = rcar_rst_read_mode_pins(&cpg_mode);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
|
||||
return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a77990_cpg_mssr_info __initconst = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r8a77990_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r8a77990_core_clks),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r8a77990_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r8a77990_mod_clks),
|
||||
.num_hw_mod_clks = 12 * 32,
|
||||
|
||||
/* Critical Module Clocks */
|
||||
.crit_mod_clks = r8a77990_crit_mod_clks,
|
||||
.num_crit_mod_clks = ARRAY_SIZE(r8a77990_crit_mod_clks),
|
||||
|
||||
/* Callbacks */
|
||||
.init = r8a77990_cpg_mssr_init,
|
||||
.cpg_clk_register = rcar_gen3_cpg_clk_register,
|
||||
};
|
||||
|
|
@ -717,6 +717,12 @@ static const struct of_device_id cpg_mssr_match[] = {
|
|||
.data = &r8a77980_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A77990
|
||||
{
|
||||
.compatible = "renesas,r8a77990-cpg-mssr",
|
||||
.data = &r8a77990_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A77995
|
||||
{
|
||||
.compatible = "renesas,r8a77995-cpg-mssr",
|
||||
|
|
|
|||
|
|
@ -143,6 +143,7 @@ extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
|
|||
extern const struct cpg_mssr_info r8a77965_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue