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gpio/rockchip: support next version gpio controller
The next version gpio controller on SoCs like rk3568 have more write mask bits for registers. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20210816012123.1119179-1-jay.xu@rock-chips.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Jianqun Xu
Linus Walleij
parent
ff96a8c21c
commit
3bcbd1a85b
2 changed files with 212 additions and 71 deletions
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@ -25,6 +25,7 @@
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#include "../pinctrl/pinctrl-rockchip.h"
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#define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
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#define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
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static const struct rockchip_gpio_regs gpio_regs_v1 = {
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.port_dr = 0x00,
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@ -40,13 +41,106 @@ static const struct rockchip_gpio_regs gpio_regs_v1 = {
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.ext_port = 0x50,
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};
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static const struct rockchip_gpio_regs gpio_regs_v2 = {
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.port_dr = 0x00,
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.port_ddr = 0x08,
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.int_en = 0x10,
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.int_mask = 0x18,
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.int_type = 0x20,
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.int_polarity = 0x28,
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.int_bothedge = 0x30,
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.int_status = 0x50,
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.int_rawstatus = 0x58,
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.debounce = 0x38,
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.dbclk_div_en = 0x40,
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.dbclk_div_con = 0x48,
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.port_eoi = 0x60,
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.ext_port = 0x70,
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.version_id = 0x78,
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};
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static inline void gpio_writel_v2(u32 val, void __iomem *reg)
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{
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writel((val & 0xffff) | 0xffff0000, reg);
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writel((val >> 16) | 0xffff0000, reg + 0x4);
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}
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static inline u32 gpio_readl_v2(void __iomem *reg)
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{
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return readl(reg + 0x4) << 16 | readl(reg);
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}
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static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
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u32 value, unsigned int offset)
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{
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void __iomem *reg = bank->reg_base + offset;
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if (bank->gpio_type == GPIO_TYPE_V2)
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gpio_writel_v2(value, reg);
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else
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writel(value, reg);
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}
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static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
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unsigned int offset)
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{
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void __iomem *reg = bank->reg_base + offset;
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u32 value;
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if (bank->gpio_type == GPIO_TYPE_V2)
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value = gpio_readl_v2(reg);
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else
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value = readl(reg);
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return value;
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}
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static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
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u32 bit, u32 value,
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unsigned int offset)
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{
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void __iomem *reg = bank->reg_base + offset;
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u32 data;
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if (bank->gpio_type == GPIO_TYPE_V2) {
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if (value)
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data = BIT(bit % 16) | BIT(bit % 16 + 16);
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else
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data = BIT(bit % 16 + 16);
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writel(data, bit >= 16 ? reg + 0x4 : reg);
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} else {
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data = readl(reg);
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data &= ~BIT(bit);
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if (value)
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data |= BIT(bit);
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writel(data, reg);
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}
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}
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static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
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u32 bit, unsigned int offset)
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{
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void __iomem *reg = bank->reg_base + offset;
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u32 data;
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if (bank->gpio_type == GPIO_TYPE_V2) {
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data = readl(bit >= 16 ? reg + 0x4 : reg);
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data >>= bit % 16;
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} else {
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data = readl(reg);
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data >>= bit;
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}
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return data & (0x1);
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}
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static int rockchip_gpio_get_direction(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
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u32 data;
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data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr);
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data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
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if (data & BIT(offset))
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return GPIO_LINE_DIRECTION_OUT;
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@ -58,18 +152,10 @@ static int rockchip_gpio_set_direction(struct gpio_chip *chip,
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
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unsigned long flags;
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u32 data;
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u32 data = input ? 0 : 1;
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr);
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/* set bit to 1 for output, 0 for input */
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if (!input)
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data |= BIT(offset);
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else
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data &= ~BIT(offset);
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writel_relaxed(data, bank->reg_base + bank->gpio_regs->port_ddr);
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rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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return 0;
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@ -79,18 +165,10 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
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int value)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
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void __iomem *reg = bank->reg_base + bank->gpio_regs->port_dr;
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unsigned long flags;
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u32 data;
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl(reg);
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data &= ~BIT(offset);
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if (value)
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data |= BIT(offset);
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writel(data, reg);
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rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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}
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@ -106,24 +184,65 @@ static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
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return data;
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}
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static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
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unsigned int offset, bool enable)
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static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
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unsigned int offset,
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unsigned int debounce)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
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void __iomem *reg = bank->reg_base + bank->gpio_regs->debounce;
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unsigned long flags;
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u32 data;
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const struct rockchip_gpio_regs *reg = bank->gpio_regs;
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unsigned long flags, div_reg, freq, max_debounce;
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bool div_debounce_support;
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unsigned int cur_div_reg;
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u64 div;
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if (!IS_ERR(bank->db_clk)) {
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div_debounce_support = true;
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freq = clk_get_rate(bank->db_clk);
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max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq;
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if (debounce > max_debounce)
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return -EINVAL;
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div = debounce * freq;
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div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1;
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} else {
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div_debounce_support = false;
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}
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl(reg);
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if (enable)
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data |= BIT(offset);
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else
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data &= ~BIT(offset);
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writel(data, reg);
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/* Only the v1 needs to configure div_en and div_con for dbclk */
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if (debounce) {
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if (div_debounce_support) {
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/* Configure the max debounce from consumers */
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cur_div_reg = readl(bank->reg_base +
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reg->dbclk_div_con);
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if (cur_div_reg < div_reg)
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writel(div_reg, bank->reg_base +
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reg->dbclk_div_con);
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rockchip_gpio_writel_bit(bank, offset, 1,
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reg->dbclk_div_en);
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}
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rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce);
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} else {
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if (div_debounce_support)
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rockchip_gpio_writel_bit(bank, offset, 0,
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reg->dbclk_div_en);
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rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce);
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}
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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/* Enable or disable dbclk at last */
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if (div_debounce_support) {
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if (debounce)
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clk_prepare_enable(bank->db_clk);
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else
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clk_disable_unprepare(bank->db_clk);
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}
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return 0;
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}
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static int rockchip_gpio_direction_input(struct gpio_chip *gc,
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@ -272,12 +391,12 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
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u32 level;
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u32 data;
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unsigned long flags;
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int ret = 0;
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr);
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data &= ~mask;
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writel_relaxed(data, bank->reg_base + bank->gpio_regs->port_ddr);
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rockchip_gpio_writel_bit(bank, d->hwirq, 0,
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bank->gpio_regs->port_ddr);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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@ -289,23 +408,30 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
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raw_spin_lock_irqsave(&bank->slock, flags);
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irq_gc_lock(gc);
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level = readl_relaxed(gc->reg_base + bank->gpio_regs->int_type);
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polarity = readl_relaxed(gc->reg_base + bank->gpio_regs->int_polarity);
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level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
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polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
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switch (type) {
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case IRQ_TYPE_EDGE_BOTH:
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if (bank->gpio_type == GPIO_TYPE_V2) {
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bank->toggle_edge_mode &= ~mask;
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rockchip_gpio_writel_bit(bank, d->hwirq, 1,
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bank->gpio_regs->int_bothedge);
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goto out;
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} else {
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bank->toggle_edge_mode |= mask;
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level |= mask;
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/*
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* Determine gpio state. If 1 next interrupt should be falling
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* otherwise rising.
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* Determine gpio state. If 1 next interrupt should be
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* falling otherwise rising.
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*/
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data = readl(bank->reg_base + bank->gpio_regs->ext_port);
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if (data & mask)
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polarity &= ~mask;
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else
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polarity |= mask;
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}
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break;
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case IRQ_TYPE_EDGE_RISING:
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bank->toggle_edge_mode &= ~mask;
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@ -328,19 +454,17 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
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polarity &= ~mask;
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break;
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default:
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irq_gc_unlock(gc);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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clk_disable(bank->clk);
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return -EINVAL;
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ret = -EINVAL;
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goto out;
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}
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writel_relaxed(level, gc->reg_base + bank->gpio_regs->int_type);
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writel_relaxed(polarity, gc->reg_base + bank->gpio_regs->int_polarity);
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rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);
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rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);
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out:
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irq_gc_unlock(gc);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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return 0;
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return ret;
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}
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static void rockchip_irq_suspend(struct irq_data *d)
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@ -362,19 +486,12 @@ static void rockchip_irq_resume(struct irq_data *d)
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static void rockchip_irq_enable(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct rockchip_pin_bank *bank = gc->private;
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irq_gc_mask_clr_bit(d);
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}
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static void rockchip_irq_disable(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct rockchip_pin_bank *bank = gc->private;
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irq_gc_mask_set_bit(d);
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clk_disable(bank->clk);
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}
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static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
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@ -403,6 +520,11 @@ static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
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}
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gc = irq_get_domain_generic_chip(bank->domain, 0);
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if (bank->gpio_type == GPIO_TYPE_V2) {
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gc->reg_writel = gpio_writel_v2;
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gc->reg_readl = gpio_readl_v2;
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}
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gc->reg_base = bank->reg_base;
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gc->private = bank;
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gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
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@ -423,9 +545,9 @@ static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
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* Our driver only uses the concept of masked and always keeps
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* things enabled, so for us that's all masked and all enabled.
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*/
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writel_relaxed(0xffffffff, bank->reg_base + bank->gpio_regs->int_mask);
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writel_relaxed(0xffffffff, bank->reg_base + bank->gpio_regs->port_eoi);
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writel_relaxed(0xffffffff, bank->reg_base + bank->gpio_regs->int_en);
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rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask);
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rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi);
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rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en);
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gc->mask_cache = 0xffffffff;
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irq_set_chained_handler_and_data(bank->irq,
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@ -503,6 +625,7 @@ static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank)
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static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
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{
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struct resource res;
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int id = 0;
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if (of_address_to_resource(bank->of_node, 0, &res)) {
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dev_err(bank->dev, "cannot find IO resource for bank\n");
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@ -514,15 +637,31 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
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return PTR_ERR(bank->reg_base);
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bank->irq = irq_of_parse_and_map(bank->of_node, 0);
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bank->gpio_regs = &gpio_regs_v1;
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bank->gpio_type = GPIO_TYPE_V1;
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if (!bank->irq)
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return -EINVAL;
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bank->clk = of_clk_get(bank->of_node, 0);
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if (!IS_ERR(bank->clk))
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return clk_prepare_enable(bank->clk);
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if (IS_ERR(bank->clk))
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return PTR_ERR(bank->clk);
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clk_prepare_enable(bank->clk);
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id = readl(bank->reg_base + gpio_regs_v2.version_id);
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/* If not gpio v2, that is default to v1. */
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if (id == GPIO_TYPE_V2) {
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bank->gpio_regs = &gpio_regs_v2;
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bank->gpio_type = GPIO_TYPE_V2;
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bank->db_clk = of_clk_get(bank->of_node, 1);
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if (IS_ERR(bank->db_clk)) {
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dev_err(bank->dev, "cannot find debounce clk\n");
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clk_disable_unprepare(bank->clk);
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return -EINVAL;
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}
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} else {
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bank->gpio_regs = &gpio_regs_v1;
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bank->gpio_type = GPIO_TYPE_V1;
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}
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bank->clk = NULL;
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return 0;
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}
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@ -121,6 +121,7 @@ struct rockchip_drv {
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* @reg_base: register base of the gpio bank
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* @regmap_pull: optional separate register for additional pull settings
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* @clk: clock of the gpio bank
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* @db_clk: clock of the gpio debounce
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* @irq: interrupt of the gpio bank
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* @saved_masks: Saved content of GPIO_INTEN at suspend time.
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* @pin_base: first pin number
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@ -146,6 +147,7 @@ struct rockchip_pin_bank {
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void __iomem *reg_base;
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struct regmap *regmap_pull;
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struct clk *clk;
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struct clk *db_clk;
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int irq;
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u32 saved_masks;
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u32 pin_base;
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