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misc: rtsx: separate aspm mode into MODE_REG and MODE_CFG

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aspm (Active State Power Management)
rtsx_comm_set_aspm: this function is for driver to make sure
not enter power saving when processing of init and card_detcct
ASPM_MODE_CFG: 8411 5209 5227 5229 5249 5250
Change back to use original way to control aspm
ASPM_MODE_REG: 5227A 524A 5250A 5260 5261 5228
Keep the new way to control aspm

Fixes: 121e9c6b5c ("misc: rtsx: modify and fix init_hw function")
Reported-by: Chris Chiu <chris.chiu@canonical.com>
Tested-by: Gordon Lack <gordon.lack@dsl.pipex.com>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Ricky Wu <ricky_wu@realtek.com>
Link: https://lore.kernel.org/r/20210607101634.4948-1-ricky_wu@realtek.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ricky Wu 2021-06-07 18:16:34 +08:00 committed by Greg Kroah-Hartman
parent 5f0c2ee1fe
commit 3df4fce739
10 changed files with 44 additions and 13 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

1
drivers/misc/cardreader/rtl8411.c
View file

@ -468,6 +468,7 @@ static void rtl8411_init_common_params(struct rtsx_pcr *pcr)
pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B; pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D; pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
pcr->aspm_en = ASPM_L1_EN; pcr->aspm_en = ASPM_L1_EN;
pcr->aspm_mode = ASPM_MODE_CFG;
pcr->tx_initial_phase = SET_CLOCK_PHASE(23, 7, 14); pcr->tx_initial_phase = SET_CLOCK_PHASE(23, 7, 14);
pcr->rx_initial_phase = SET_CLOCK_PHASE(4, 3, 10); pcr->rx_initial_phase = SET_CLOCK_PHASE(4, 3, 10);
pcr->ic_version = rtl8411_get_ic_version(pcr); pcr->ic_version = rtl8411_get_ic_version(pcr);

1
drivers/misc/cardreader/rts5209.c
View file

@ -255,6 +255,7 @@ void rts5209_init_params(struct rtsx_pcr *pcr)
pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B; pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D; pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
pcr->aspm_en = ASPM_L1_EN; pcr->aspm_en = ASPM_L1_EN;
pcr->aspm_mode = ASPM_MODE_CFG;
pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 16); pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 16);
pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);

2
drivers/misc/cardreader/rts5227.c
View file

@ -358,6 +358,7 @@ void rts5227_init_params(struct rtsx_pcr *pcr)
pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
pcr->aspm_en = ASPM_L1_EN; pcr->aspm_en = ASPM_L1_EN;
pcr->aspm_mode = ASPM_MODE_CFG;
pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15); pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7); pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
@ -483,6 +484,7 @@ void rts522a_init_params(struct rtsx_pcr *pcr)
rts5227_init_params(pcr); rts5227_init_params(pcr);
pcr->ops = &rts522a_pcr_ops; pcr->ops = &rts522a_pcr_ops;
pcr->aspm_mode = ASPM_MODE_REG;
pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11); pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3; pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;

1
drivers/misc/cardreader/rts5228.c
View file

@ -718,6 +718,7 @@ void rts5228_init_params(struct rtsx_pcr *pcr)
pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
pcr->aspm_en = ASPM_L1_EN; pcr->aspm_en = ASPM_L1_EN;
pcr->aspm_mode = ASPM_MODE_REG;
pcr->tx_initial_phase = SET_CLOCK_PHASE(28, 27, 11); pcr->tx_initial_phase = SET_CLOCK_PHASE(28, 27, 11);
pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);

1
drivers/misc/cardreader/rts5229.c
View file

@ -246,6 +246,7 @@ void rts5229_init_params(struct rtsx_pcr *pcr)
pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B; pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D; pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
pcr->aspm_en = ASPM_L1_EN; pcr->aspm_en = ASPM_L1_EN;
pcr->aspm_mode = ASPM_MODE_CFG;
pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15); pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 6, 6); pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 6, 6);

3
drivers/misc/cardreader/rts5249.c
View file

@ -566,6 +566,7 @@ void rts5249_init_params(struct rtsx_pcr *pcr)
pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
pcr->aspm_en = ASPM_L1_EN; pcr->aspm_en = ASPM_L1_EN;
pcr->aspm_mode = ASPM_MODE_CFG;
pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16); pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
@ -729,6 +730,7 @@ static const struct pcr_ops rts524a_pcr_ops = {
void rts524a_init_params(struct rtsx_pcr *pcr) void rts524a_init_params(struct rtsx_pcr *pcr)
{ {
rts5249_init_params(pcr); rts5249_init_params(pcr);
pcr->aspm_mode = ASPM_MODE_REG;
pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11); pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
pcr->option.ltr_l1off_snooze_sspwrgate = pcr->option.ltr_l1off_snooze_sspwrgate =
@ -845,6 +847,7 @@ static const struct pcr_ops rts525a_pcr_ops = {
void rts525a_init_params(struct rtsx_pcr *pcr) void rts525a_init_params(struct rtsx_pcr *pcr)
{ {
rts5249_init_params(pcr); rts5249_init_params(pcr);
pcr->aspm_mode = ASPM_MODE_REG;
pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11); pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11);
pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
pcr->option.ltr_l1off_snooze_sspwrgate = pcr->option.ltr_l1off_snooze_sspwrgate =

1
drivers/misc/cardreader/rts5260.c
View file

@ -628,6 +628,7 @@ void rts5260_init_params(struct rtsx_pcr *pcr)
pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
pcr->aspm_en = ASPM_L1_EN; pcr->aspm_en = ASPM_L1_EN;
pcr->aspm_mode = ASPM_MODE_REG;
pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11); pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);

1
drivers/misc/cardreader/rts5261.c
View file

@ -783,6 +783,7 @@ void rts5261_init_params(struct rtsx_pcr *pcr)
pcr->sd30_drive_sel_1v8 = 0x00; pcr->sd30_drive_sel_1v8 = 0x00;
pcr->sd30_drive_sel_3v3 = 0x00; pcr->sd30_drive_sel_3v3 = 0x00;
pcr->aspm_en = ASPM_L1_EN; pcr->aspm_en = ASPM_L1_EN;
pcr->aspm_mode = ASPM_MODE_REG;
pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11); pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11);
pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);

44
drivers/misc/cardreader/rtsx_pcr.c
View file

@ -85,12 +85,18 @@ static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable)
if (pcr->aspm_enabled == enable) if (pcr->aspm_enabled == enable)
return; return;
if (pcr->aspm_en & 0x02) if (pcr->aspm_mode == ASPM_MODE_CFG) {
rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 | pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
FORCE_ASPM_CTL1, enable ? 0 : FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1); PCI_EXP_LNKCTL_ASPMC,
else enable ? pcr->aspm_en : 0);
rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 | } else if (pcr->aspm_mode == ASPM_MODE_REG) {
FORCE_ASPM_CTL1, FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1); if (pcr->aspm_en & 0x02)
rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 |
FORCE_ASPM_CTL1, enable ? 0 : FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1);
else
rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 |
FORCE_ASPM_CTL1, FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1);
}
if (!enable && (pcr->aspm_en & 0x02)) if (!enable && (pcr->aspm_en & 0x02))
mdelay(10); mdelay(10);
@ -1394,7 +1400,8 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
return err; return err;
} }
rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30); if (pcr->aspm_mode == ASPM_MODE_REG)
rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30);
/* No CD interrupt if probing driver with card inserted. /* No CD interrupt if probing driver with card inserted.
* So we need to initialize pcr->card_exist here. * So we need to initialize pcr->card_exist here.
@ -1410,6 +1417,8 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
{ {
int err; int err;
u16 cfg_val;
u8 val;
spin_lock_init(&pcr->lock); spin_lock_init(&pcr->lock);
mutex_init(&pcr->pcr_mutex); mutex_init(&pcr->pcr_mutex);
@ -1477,6 +1486,21 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
if (!pcr->slots) if (!pcr->slots)
return -ENOMEM; return -ENOMEM;
if (pcr->aspm_mode == ASPM_MODE_CFG) {
pcie_capability_read_word(pcr->pci, PCI_EXP_LNKCTL, &cfg_val);
if (cfg_val & PCI_EXP_LNKCTL_ASPM_L1)
pcr->aspm_enabled = true;
else
pcr->aspm_enabled = false;
} else if (pcr->aspm_mode == ASPM_MODE_REG) {
rtsx_pci_read_register(pcr, ASPM_FORCE_CTL, &val);
if (val & FORCE_ASPM_CTL0 && val & FORCE_ASPM_CTL1)
pcr->aspm_enabled = false;
else
pcr->aspm_enabled = true;
}
if (pcr->ops->fetch_vendor_settings) if (pcr->ops->fetch_vendor_settings)
pcr->ops->fetch_vendor_settings(pcr); pcr->ops->fetch_vendor_settings(pcr);
@ -1506,7 +1530,6 @@ static int rtsx_pci_probe(struct pci_dev *pcidev,
struct pcr_handle *handle; struct pcr_handle *handle;
u32 base, len; u32 base, len;
int ret, i, bar = 0; int ret, i, bar = 0;
u8 val;
dev_dbg(&(pcidev->dev), dev_dbg(&(pcidev->dev),
": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n", ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
@ -1572,11 +1595,6 @@ static int rtsx_pci_probe(struct pci_dev *pcidev,
pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr; pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN; pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN; pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
rtsx_pci_read_register(pcr, ASPM_FORCE_CTL, &val);
if (val & FORCE_ASPM_CTL0 && val & FORCE_ASPM_CTL1)
pcr->aspm_enabled = false;
else
pcr->aspm_enabled = true;
pcr->card_inserted = 0; pcr->card_inserted = 0;
pcr->card_removed = 0; pcr->card_removed = 0;
INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect); INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);

2
include/linux/rtsx_pci.h
View file

@ -1109,6 +1109,7 @@ struct pcr_ops {
}; };
enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN}; enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN};
enum ASPM_MODE {ASPM_MODE_CFG, ASPM_MODE_REG};
#define ASPM_L1_1_EN BIT(0) #define ASPM_L1_1_EN BIT(0)
#define ASPM_L1_2_EN BIT(1) #define ASPM_L1_2_EN BIT(1)
@ -1234,6 +1235,7 @@ struct rtsx_pcr {
u8 card_drive_sel; u8 card_drive_sel;
#define ASPM_L1_EN 0x02 #define ASPM_L1_EN 0x02
u8 aspm_en; u8 aspm_en;
enum ASPM_MODE aspm_mode;
bool aspm_enabled; bool aspm_enabled;
#define PCR_MS_PMOS (1 << 0) #define PCR_MS_PMOS (1 << 0)