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	pwm: mtk-disp: Implement atomic API .get_state()
Switch the driver to support the .get_state() method. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> [thierry.reding@gmail.com: add missing linux/bitfield.h include] Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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			@ -5,6 +5,7 @@
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 * Author: YH Huang <yh.huang@mediatek.com>
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 */
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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			@ -171,8 +172,50 @@ static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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	return 0;
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}
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static void mtk_disp_pwm_get_state(struct pwm_chip *chip,
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				   struct pwm_device *pwm,
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				   struct pwm_state *state)
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{
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	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
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	u64 rate, period, high_width;
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	u32 clk_div, con0, con1;
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	int err;
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	err = clk_prepare_enable(mdp->clk_main);
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	if (err < 0) {
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		dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
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		return;
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	}
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	err = clk_prepare_enable(mdp->clk_mm);
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	if (err < 0) {
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		dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
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		clk_disable_unprepare(mdp->clk_main);
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		return;
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	}
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	rate = clk_get_rate(mdp->clk_main);
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	con0 = readl(mdp->base + mdp->data->con0);
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	con1 = readl(mdp->base + mdp->data->con1);
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	state->enabled = !!(con0 & BIT(0));
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	clk_div = FIELD_GET(PWM_CLKDIV_MASK, con0);
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	period = FIELD_GET(PWM_PERIOD_MASK, con1);
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	/*
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	 * period has 12 bits, clk_div 11 and NSEC_PER_SEC has 30,
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	 * so period * (clk_div + 1) * NSEC_PER_SEC doesn't overflow.
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	 */
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	state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate);
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	high_width = FIELD_GET(PWM_HIGH_WIDTH_MASK, con1);
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	state->duty_cycle = DIV64_U64_ROUND_UP(high_width * (clk_div + 1) * NSEC_PER_SEC,
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					       rate);
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	state->polarity = PWM_POLARITY_NORMAL;
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	clk_disable_unprepare(mdp->clk_mm);
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	clk_disable_unprepare(mdp->clk_main);
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}
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static const struct pwm_ops mtk_disp_pwm_ops = {
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	.apply = mtk_disp_pwm_apply,
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	.get_state = mtk_disp_pwm_get_state,
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	.owner = THIS_MODULE,
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};
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