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MIPS/OCTEON/ata: Convert pata_octeon_cf.c to use device tree.
The patch needs to eliminate the definition of OCTEON_IRQ_BOOTDMA so that the device tree code can map the interrupt, so in order to not temporarily break things, we do a single patch to both the interrupt registration code and the pata_octeon_cf driver. Also rolled in is a conversion to use hrtimers and corrections to the timing calculations. Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: David Daney <david.daney@cavium.com>
This commit is contained in:
David Daney
Ralf Baechle
parent
f772cdb2bd
commit
43f01da0f2
5 changed files with 288 additions and 250 deletions
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@ -1266,7 +1266,6 @@ static void __init octeon_irq_init_ciu(void)
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octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_TIMER0, 0, i + 52);
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octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 0, 56);
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octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_BOOTDMA, 0, 63);
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/* CIU_1 */
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for (i = 0; i < 16; i++)
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@ -24,108 +24,6 @@
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#include <asm/octeon/cvmx-helper.h>
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#include <asm/octeon/cvmx-helper-board.h>
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static struct octeon_cf_data octeon_cf_data;
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static int __init octeon_cf_device_init(void)
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{
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union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
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unsigned long base_ptr, region_base, region_size;
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struct platform_device *pd;
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struct resource cf_resources[3];
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unsigned int num_resources;
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int i;
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int ret = 0;
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/* Setup octeon-cf platform device if present. */
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base_ptr = 0;
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if (octeon_bootinfo->major_version == 1
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&& octeon_bootinfo->minor_version >= 1) {
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if (octeon_bootinfo->compact_flash_common_base_addr)
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base_ptr =
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octeon_bootinfo->compact_flash_common_base_addr;
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} else {
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base_ptr = 0x1d000800;
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}
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if (!base_ptr)
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return ret;
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/* Find CS0 region. */
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for (i = 0; i < 8; i++) {
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mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
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region_base = mio_boot_reg_cfg.s.base << 16;
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region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
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if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
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&& base_ptr < region_base + region_size)
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break;
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}
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if (i >= 7) {
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/* i and i + 1 are CS0 and CS1, both must be less than 8. */
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goto out;
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}
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octeon_cf_data.base_region = i;
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octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
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octeon_cf_data.base_region_bias = base_ptr - region_base;
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memset(cf_resources, 0, sizeof(cf_resources));
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num_resources = 0;
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cf_resources[num_resources].flags = IORESOURCE_MEM;
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cf_resources[num_resources].start = region_base;
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cf_resources[num_resources].end = region_base + region_size - 1;
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num_resources++;
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if (!(base_ptr & 0xfffful)) {
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/*
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* Boot loader signals availability of DMA (true_ide
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* mode) by setting low order bits of base_ptr to
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* zero.
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*/
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/* Assume that CS1 immediately follows. */
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mio_boot_reg_cfg.u64 =
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cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
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region_base = mio_boot_reg_cfg.s.base << 16;
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region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
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if (!mio_boot_reg_cfg.s.en)
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goto out;
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cf_resources[num_resources].flags = IORESOURCE_MEM;
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cf_resources[num_resources].start = region_base;
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cf_resources[num_resources].end = region_base + region_size - 1;
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num_resources++;
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octeon_cf_data.dma_engine = 0;
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cf_resources[num_resources].flags = IORESOURCE_IRQ;
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cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
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cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
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num_resources++;
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} else {
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octeon_cf_data.dma_engine = -1;
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}
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pd = platform_device_alloc("pata_octeon_cf", -1);
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if (!pd) {
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ret = -ENOMEM;
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goto out;
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}
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pd->dev.platform_data = &octeon_cf_data;
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ret = platform_device_add_resources(pd, cf_resources, num_resources);
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if (ret)
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goto fail;
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ret = platform_device_add(pd);
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if (ret)
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goto fail;
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return ret;
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fail:
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platform_device_put(pd);
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out:
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return ret;
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}
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device_initcall(octeon_cf_device_init);
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/* Octeon Random Number Generator. */
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static int __init octeon_rng_device_init(void)
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{
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@ -42,7 +42,6 @@ enum octeon_irq {
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OCTEON_IRQ_TIMER3,
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OCTEON_IRQ_USB0,
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OCTEON_IRQ_USB1,
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OCTEON_IRQ_BOOTDMA,
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#ifndef CONFIG_PCI_MSI
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OCTEON_IRQ_LAST = 127
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#endif
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@ -209,13 +209,6 @@ union octeon_cvmemctl {
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} s;
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};
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struct octeon_cf_data {
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unsigned long base_region_bias;
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unsigned int base_region; /* The chip select region used by CF */
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int is16bit; /* 0 - 8bit, !0 - 16bit */
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int dma_engine; /* -1 for no DMA */
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};
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extern void octeon_write_lcd(const char *s);
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extern void octeon_check_cpu_bist(void);
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extern int octeon_get_boot_debug_flag(void);
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@ -5,17 +5,19 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2005 - 2009 Cavium Networks
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* Copyright (C) 2005 - 2012 Cavium Inc.
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* Copyright (C) 2008 Wind River Systems
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/libata.h>
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#include <linux/irq.h>
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#include <linux/hrtimer.h>
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#include <linux/slab.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/workqueue.h>
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#include <scsi/scsi_host.h>
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#include <asm/octeon/octeon.h>
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@ -34,20 +36,36 @@
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*/
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#define DRV_NAME "pata_octeon_cf"
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#define DRV_VERSION "2.1"
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#define DRV_VERSION "2.2"
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/* Poll interval in nS. */
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#define OCTEON_CF_BUSY_POLL_INTERVAL 500000
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#define DMA_CFG 0
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#define DMA_TIM 0x20
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#define DMA_INT 0x38
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#define DMA_INT_EN 0x50
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struct octeon_cf_port {
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struct workqueue_struct *wq;
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struct delayed_work delayed_finish;
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struct hrtimer delayed_finish;
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struct ata_port *ap;
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int dma_finished;
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void *c0;
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unsigned int cs0;
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unsigned int cs1;
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bool is_true_ide;
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u64 dma_base;
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};
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static struct scsi_host_template octeon_cf_sht = {
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ATA_PIO_SHT(DRV_NAME),
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};
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static int enable_dma;
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module_param(enable_dma, int, 0444);
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MODULE_PARM_DESC(enable_dma,
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"Enable use of DMA on interfaces that support it (0=no dma [default], 1=use dma)");
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/**
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* Convert nanosecond based time to setting used in the
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* boot bus timing register, based on timing multiple
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@ -66,12 +84,29 @@ static unsigned int ns_to_tim_reg(unsigned int tim_mult, unsigned int nsecs)
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return val;
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}
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static void octeon_cf_set_boot_reg_cfg(int cs)
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static void octeon_cf_set_boot_reg_cfg(int cs, unsigned int multiplier)
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{
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union cvmx_mio_boot_reg_cfgx reg_cfg;
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unsigned int tim_mult;
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switch (multiplier) {
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case 8:
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tim_mult = 3;
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break;
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case 4:
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tim_mult = 0;
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break;
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case 2:
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tim_mult = 2;
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break;
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default:
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tim_mult = 1;
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break;
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}
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reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
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reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */
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reg_cfg.s.tim_mult = 2; /* Timing mutiplier 2x */
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reg_cfg.s.tim_mult = tim_mult; /* Timing mutiplier */
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reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */
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reg_cfg.s.sam = 0; /* Don't combine write and output enable */
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reg_cfg.s.we_ext = 0; /* No write enable extension */
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@ -92,12 +127,12 @@ static void octeon_cf_set_boot_reg_cfg(int cs)
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*/
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static void octeon_cf_set_piomode(struct ata_port *ap, struct ata_device *dev)
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{
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struct octeon_cf_data *ocd = ap->dev->platform_data;
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struct octeon_cf_port *cf_port = ap->private_data;
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union cvmx_mio_boot_reg_timx reg_tim;
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int cs = ocd->base_region;
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int T;
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struct ata_timing timing;
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unsigned int div;
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int use_iordy;
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int trh;
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int pause;
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@ -106,7 +141,15 @@ static void octeon_cf_set_piomode(struct ata_port *ap, struct ata_device *dev)
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int t2;
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int t2i;
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T = (int)(2000000000000LL / octeon_get_clock_rate());
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/*
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* A divisor value of four will overflow the timing fields at
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* clock rates greater than 800MHz
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*/
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if (octeon_get_io_clock_rate() <= 800000000)
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div = 4;
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else
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div = 8;
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T = (int)((1000000000000LL * div) / octeon_get_io_clock_rate());
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if (ata_timing_compute(dev, dev->pio_mode, &timing, T, T))
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BUG();
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@ -121,23 +164,26 @@ static void octeon_cf_set_piomode(struct ata_port *ap, struct ata_device *dev)
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if (t2i)
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t2i--;
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trh = ns_to_tim_reg(2, 20);
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trh = ns_to_tim_reg(div, 20);
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if (trh)
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trh--;
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pause = timing.cycle - timing.active - timing.setup - trh;
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pause = (int)timing.cycle - (int)timing.active -
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(int)timing.setup - trh;
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if (pause < 0)
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pause = 0;
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if (pause)
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pause--;
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octeon_cf_set_boot_reg_cfg(cs);
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if (ocd->dma_engine >= 0)
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octeon_cf_set_boot_reg_cfg(cf_port->cs0, div);
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if (cf_port->is_true_ide)
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/* True IDE mode, program both chip selects. */
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octeon_cf_set_boot_reg_cfg(cs + 1);
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octeon_cf_set_boot_reg_cfg(cf_port->cs1, div);
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use_iordy = ata_pio_need_iordy(dev);
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reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cs));
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reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0));
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/* Disable page mode */
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reg_tim.s.pagem = 0;
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/* Enable dynamic timing */
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@ -161,20 +207,22 @@ static void octeon_cf_set_piomode(struct ata_port *ap, struct ata_device *dev)
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/* How long read enable is asserted */
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reg_tim.s.oe = t2;
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/* Time after CE that read/write starts */
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reg_tim.s.ce = ns_to_tim_reg(2, 5);
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reg_tim.s.ce = ns_to_tim_reg(div, 5);
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/* Time before CE that address is valid */
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reg_tim.s.adr = 0;
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/* Program the bootbus region timing for the data port chip select. */
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cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cs), reg_tim.u64);
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if (ocd->dma_engine >= 0)
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cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0), reg_tim.u64);
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if (cf_port->is_true_ide)
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/* True IDE mode, program both chip selects. */
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cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cs + 1), reg_tim.u64);
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cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs1),
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reg_tim.u64);
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}
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static void octeon_cf_set_dmamode(struct ata_port *ap, struct ata_device *dev)
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{
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struct octeon_cf_data *ocd = dev->link->ap->dev->platform_data;
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struct octeon_cf_port *cf_port = ap->private_data;
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union cvmx_mio_boot_pin_defs pin_defs;
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union cvmx_mio_boot_dma_timx dma_tim;
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unsigned int oe_a;
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unsigned int oe_n;
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@ -183,6 +231,7 @@ static void octeon_cf_set_dmamode(struct ata_port *ap, struct ata_device *dev)
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unsigned int pause;
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unsigned int T0, Tkr, Td;
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unsigned int tim_mult;
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int c;
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const struct ata_timing *timing;
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@ -199,13 +248,19 @@ static void octeon_cf_set_dmamode(struct ata_port *ap, struct ata_device *dev)
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/* not spec'ed, value in eclocks, not affected by tim_mult */
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dma_arq = 8;
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pause = 25 - dma_arq * 1000 /
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(octeon_get_clock_rate() / 1000000); /* Tz */
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(octeon_get_io_clock_rate() / 1000000); /* Tz */
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oe_a = Td;
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/* Tkr from cf spec, lengthened to meet T0 */
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oe_n = max(T0 - oe_a, Tkr);
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dma_tim.s.dmack_pi = 1;
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pin_defs.u64 = cvmx_read_csr(CVMX_MIO_BOOT_PIN_DEFS);
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/* DMA channel number. */
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c = (cf_port->dma_base & 8) >> 3;
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/* Invert the polarity if the default is 0*/
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dma_tim.s.dmack_pi = (pin_defs.u64 & (1ull << (11 + c))) ? 0 : 1;
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dma_tim.s.oe_n = ns_to_tim_reg(tim_mult, oe_n);
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dma_tim.s.oe_a = ns_to_tim_reg(tim_mult, oe_a);
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@ -228,14 +283,11 @@ static void octeon_cf_set_dmamode(struct ata_port *ap, struct ata_device *dev)
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pr_debug("ns to ticks (mult %d) of %d is: %d\n", tim_mult, 60,
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ns_to_tim_reg(tim_mult, 60));
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pr_debug("oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: "
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"%d, dmarq: %d, pause: %d\n",
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pr_debug("oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: %d, dmarq: %d, pause: %d\n",
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dma_tim.s.oe_n, dma_tim.s.oe_a, dma_tim.s.dmack_s,
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dma_tim.s.dmack_h, dma_tim.s.dmarq, dma_tim.s.pause);
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cvmx_write_csr(CVMX_MIO_BOOT_DMA_TIMX(ocd->dma_engine),
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dma_tim.u64);
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cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64);
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}
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/**
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@ -489,15 +541,10 @@ static void octeon_cf_exec_command16(struct ata_port *ap,
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ata_wait_idle(ap);
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}
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static void octeon_cf_irq_on(struct ata_port *ap)
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static void octeon_cf_ata_port_noaction(struct ata_port *ap)
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{
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}
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static void octeon_cf_irq_clear(struct ata_port *ap)
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{
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return;
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}
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static void octeon_cf_dma_setup(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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@ -519,7 +566,7 @@ static void octeon_cf_dma_setup(struct ata_queued_cmd *qc)
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*/
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static void octeon_cf_dma_start(struct ata_queued_cmd *qc)
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{
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struct octeon_cf_data *ocd = qc->ap->dev->platform_data;
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struct octeon_cf_port *cf_port = qc->ap->private_data;
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union cvmx_mio_boot_dma_cfgx mio_boot_dma_cfg;
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union cvmx_mio_boot_dma_intx mio_boot_dma_int;
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struct scatterlist *sg;
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|
@ -535,12 +582,10 @@ static void octeon_cf_dma_start(struct ata_queued_cmd *qc)
|
|||
*/
|
||||
mio_boot_dma_int.u64 = 0;
|
||||
mio_boot_dma_int.s.done = 1;
|
||||
cvmx_write_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine),
|
||||
mio_boot_dma_int.u64);
|
||||
cvmx_write_csr(cf_port->dma_base + DMA_INT, mio_boot_dma_int.u64);
|
||||
|
||||
/* Enable the interrupt. */
|
||||
cvmx_write_csr(CVMX_MIO_BOOT_DMA_INT_ENX(ocd->dma_engine),
|
||||
mio_boot_dma_int.u64);
|
||||
cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, mio_boot_dma_int.u64);
|
||||
|
||||
/* Set the direction of the DMA */
|
||||
mio_boot_dma_cfg.u64 = 0;
|
||||
|
|
@ -569,8 +614,7 @@ static void octeon_cf_dma_start(struct ata_queued_cmd *qc)
|
|||
(mio_boot_dma_cfg.s.rw) ? "write" : "read", sg->length,
|
||||
(void *)(unsigned long)mio_boot_dma_cfg.s.adr);
|
||||
|
||||
cvmx_write_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine),
|
||||
mio_boot_dma_cfg.u64);
|
||||
cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -583,10 +627,9 @@ static unsigned int octeon_cf_dma_finished(struct ata_port *ap,
|
|||
struct ata_queued_cmd *qc)
|
||||
{
|
||||
struct ata_eh_info *ehi = &ap->link.eh_info;
|
||||
struct octeon_cf_data *ocd = ap->dev->platform_data;
|
||||
struct octeon_cf_port *cf_port = ap->private_data;
|
||||
union cvmx_mio_boot_dma_cfgx dma_cfg;
|
||||
union cvmx_mio_boot_dma_intx dma_int;
|
||||
struct octeon_cf_port *cf_port;
|
||||
u8 status;
|
||||
|
||||
VPRINTK("ata%u: protocol %d task_state %d\n",
|
||||
|
|
@ -596,9 +639,7 @@ static unsigned int octeon_cf_dma_finished(struct ata_port *ap,
|
|||
if (ap->hsm_task_state != HSM_ST_LAST)
|
||||
return 0;
|
||||
|
||||
cf_port = ap->private_data;
|
||||
|
||||
dma_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine));
|
||||
dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
|
||||
if (dma_cfg.s.size != 0xfffff) {
|
||||
/* Error, the transfer was not complete. */
|
||||
qc->err_mask |= AC_ERR_HOST_BUS;
|
||||
|
|
@ -608,15 +649,15 @@ static unsigned int octeon_cf_dma_finished(struct ata_port *ap,
|
|||
/* Stop and clear the dma engine. */
|
||||
dma_cfg.u64 = 0;
|
||||
dma_cfg.s.size = -1;
|
||||
cvmx_write_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine), dma_cfg.u64);
|
||||
cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
|
||||
|
||||
/* Disable the interrupt. */
|
||||
dma_int.u64 = 0;
|
||||
cvmx_write_csr(CVMX_MIO_BOOT_DMA_INT_ENX(ocd->dma_engine), dma_int.u64);
|
||||
cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
|
||||
|
||||
/* Clear the DMA complete status */
|
||||
dma_int.s.done = 1;
|
||||
cvmx_write_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine), dma_int.u64);
|
||||
cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
|
||||
|
||||
status = ap->ops->sff_check_status(ap);
|
||||
|
||||
|
|
@ -649,69 +690,68 @@ static irqreturn_t octeon_cf_interrupt(int irq, void *dev_instance)
|
|||
struct ata_queued_cmd *qc;
|
||||
union cvmx_mio_boot_dma_intx dma_int;
|
||||
union cvmx_mio_boot_dma_cfgx dma_cfg;
|
||||
struct octeon_cf_data *ocd;
|
||||
|
||||
ap = host->ports[i];
|
||||
ocd = ap->dev->platform_data;
|
||||
cf_port = ap->private_data;
|
||||
dma_int.u64 =
|
||||
cvmx_read_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine));
|
||||
dma_cfg.u64 =
|
||||
cvmx_read_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine));
|
||||
|
||||
dma_int.u64 = cvmx_read_csr(cf_port->dma_base + DMA_INT);
|
||||
dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
|
||||
|
||||
qc = ata_qc_from_tag(ap, ap->link.active_tag);
|
||||
|
||||
if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING)) {
|
||||
if (dma_int.s.done && !dma_cfg.s.en) {
|
||||
if (!sg_is_last(qc->cursg)) {
|
||||
qc->cursg = sg_next(qc->cursg);
|
||||
handled = 1;
|
||||
octeon_cf_dma_start(qc);
|
||||
continue;
|
||||
} else {
|
||||
cf_port->dma_finished = 1;
|
||||
}
|
||||
}
|
||||
if (!cf_port->dma_finished)
|
||||
continue;
|
||||
status = ioread8(ap->ioaddr.altstatus_addr);
|
||||
if (status & (ATA_BUSY | ATA_DRQ)) {
|
||||
/*
|
||||
* We are busy, try to handle it
|
||||
* later. This is the DMA finished
|
||||
* interrupt, and it could take a
|
||||
* little while for the card to be
|
||||
* ready for more commands.
|
||||
*/
|
||||
/* Clear DMA irq. */
|
||||
dma_int.u64 = 0;
|
||||
dma_int.s.done = 1;
|
||||
cvmx_write_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine),
|
||||
dma_int.u64);
|
||||
if (!qc || (qc->tf.flags & ATA_TFLAG_POLLING))
|
||||
continue;
|
||||
|
||||
queue_delayed_work(cf_port->wq,
|
||||
&cf_port->delayed_finish, 1);
|
||||
if (dma_int.s.done && !dma_cfg.s.en) {
|
||||
if (!sg_is_last(qc->cursg)) {
|
||||
qc->cursg = sg_next(qc->cursg);
|
||||
handled = 1;
|
||||
octeon_cf_dma_start(qc);
|
||||
continue;
|
||||
} else {
|
||||
handled |= octeon_cf_dma_finished(ap, qc);
|
||||
cf_port->dma_finished = 1;
|
||||
}
|
||||
}
|
||||
if (!cf_port->dma_finished)
|
||||
continue;
|
||||
status = ioread8(ap->ioaddr.altstatus_addr);
|
||||
if (status & (ATA_BUSY | ATA_DRQ)) {
|
||||
/*
|
||||
* We are busy, try to handle it later. This
|
||||
* is the DMA finished interrupt, and it could
|
||||
* take a little while for the card to be
|
||||
* ready for more commands.
|
||||
*/
|
||||
/* Clear DMA irq. */
|
||||
dma_int.u64 = 0;
|
||||
dma_int.s.done = 1;
|
||||
cvmx_write_csr(cf_port->dma_base + DMA_INT,
|
||||
dma_int.u64);
|
||||
hrtimer_start_range_ns(&cf_port->delayed_finish,
|
||||
ns_to_ktime(OCTEON_CF_BUSY_POLL_INTERVAL),
|
||||
OCTEON_CF_BUSY_POLL_INTERVAL / 5,
|
||||
HRTIMER_MODE_REL);
|
||||
handled = 1;
|
||||
} else {
|
||||
handled |= octeon_cf_dma_finished(ap, qc);
|
||||
}
|
||||
}
|
||||
spin_unlock_irqrestore(&host->lock, flags);
|
||||
DPRINTK("EXIT\n");
|
||||
return IRQ_RETVAL(handled);
|
||||
}
|
||||
|
||||
static void octeon_cf_delayed_finish(struct work_struct *work)
|
||||
static enum hrtimer_restart octeon_cf_delayed_finish(struct hrtimer *hrt)
|
||||
{
|
||||
struct octeon_cf_port *cf_port = container_of(work,
|
||||
struct octeon_cf_port *cf_port = container_of(hrt,
|
||||
struct octeon_cf_port,
|
||||
delayed_finish.work);
|
||||
delayed_finish);
|
||||
struct ata_port *ap = cf_port->ap;
|
||||
struct ata_host *host = ap->host;
|
||||
struct ata_queued_cmd *qc;
|
||||
unsigned long flags;
|
||||
u8 status;
|
||||
enum hrtimer_restart rv = HRTIMER_NORESTART;
|
||||
|
||||
spin_lock_irqsave(&host->lock, flags);
|
||||
|
||||
|
|
@ -726,15 +766,17 @@ static void octeon_cf_delayed_finish(struct work_struct *work)
|
|||
status = ioread8(ap->ioaddr.altstatus_addr);
|
||||
if (status & (ATA_BUSY | ATA_DRQ)) {
|
||||
/* Still busy, try again. */
|
||||
queue_delayed_work(cf_port->wq,
|
||||
&cf_port->delayed_finish, 1);
|
||||
hrtimer_forward_now(hrt,
|
||||
ns_to_ktime(OCTEON_CF_BUSY_POLL_INTERVAL));
|
||||
rv = HRTIMER_RESTART;
|
||||
goto out;
|
||||
}
|
||||
qc = ata_qc_from_tag(ap, ap->link.active_tag);
|
||||
if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
|
||||
if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
|
||||
octeon_cf_dma_finished(ap, qc);
|
||||
out:
|
||||
spin_unlock_irqrestore(&host->lock, flags);
|
||||
return rv;
|
||||
}
|
||||
|
||||
static void octeon_cf_dev_config(struct ata_device *dev)
|
||||
|
|
@ -786,8 +828,8 @@ static struct ata_port_operations octeon_cf_ops = {
|
|||
.qc_prep = ata_noop_qc_prep,
|
||||
.qc_issue = octeon_cf_qc_issue,
|
||||
.sff_dev_select = octeon_cf_dev_select,
|
||||
.sff_irq_on = octeon_cf_irq_on,
|
||||
.sff_irq_clear = octeon_cf_irq_clear,
|
||||
.sff_irq_on = octeon_cf_ata_port_noaction,
|
||||
.sff_irq_clear = octeon_cf_ata_port_noaction,
|
||||
.cable_detect = ata_cable_40wire,
|
||||
.set_piomode = octeon_cf_set_piomode,
|
||||
.set_dmamode = octeon_cf_set_dmamode,
|
||||
|
|
@ -798,46 +840,113 @@ static int __devinit octeon_cf_probe(struct platform_device *pdev)
|
|||
{
|
||||
struct resource *res_cs0, *res_cs1;
|
||||
|
||||
bool is_16bit;
|
||||
const __be32 *cs_num;
|
||||
struct property *reg_prop;
|
||||
int n_addr, n_size, reg_len;
|
||||
struct device_node *node;
|
||||
const void *prop;
|
||||
void __iomem *cs0;
|
||||
void __iomem *cs1 = NULL;
|
||||
struct ata_host *host;
|
||||
struct ata_port *ap;
|
||||
struct octeon_cf_data *ocd;
|
||||
int irq = 0;
|
||||
irq_handler_t irq_handler = NULL;
|
||||
void __iomem *base;
|
||||
struct octeon_cf_port *cf_port;
|
||||
char version[32];
|
||||
int rv = -ENOMEM;
|
||||
|
||||
|
||||
node = pdev->dev.of_node;
|
||||
if (node == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
cf_port = kzalloc(sizeof(*cf_port), GFP_KERNEL);
|
||||
if (!cf_port)
|
||||
return -ENOMEM;
|
||||
|
||||
cf_port->is_true_ide = (of_find_property(node, "cavium,true-ide", NULL) != NULL);
|
||||
|
||||
prop = of_get_property(node, "cavium,bus-width", NULL);
|
||||
if (prop)
|
||||
is_16bit = (be32_to_cpup(prop) == 16);
|
||||
else
|
||||
is_16bit = false;
|
||||
|
||||
n_addr = of_n_addr_cells(node);
|
||||
n_size = of_n_size_cells(node);
|
||||
|
||||
reg_prop = of_find_property(node, "reg", ®_len);
|
||||
if (!reg_prop || reg_len < sizeof(__be32)) {
|
||||
rv = -EINVAL;
|
||||
goto free_cf_port;
|
||||
}
|
||||
cs_num = reg_prop->value;
|
||||
cf_port->cs0 = be32_to_cpup(cs_num);
|
||||
|
||||
if (cf_port->is_true_ide) {
|
||||
struct device_node *dma_node;
|
||||
dma_node = of_parse_phandle(node,
|
||||
"cavium,dma-engine-handle", 0);
|
||||
if (dma_node) {
|
||||
struct platform_device *dma_dev;
|
||||
dma_dev = of_find_device_by_node(dma_node);
|
||||
if (dma_dev) {
|
||||
struct resource *res_dma;
|
||||
int i;
|
||||
res_dma = platform_get_resource(dma_dev, IORESOURCE_MEM, 0);
|
||||
if (!res_dma) {
|
||||
of_node_put(dma_node);
|
||||
rv = -EINVAL;
|
||||
goto free_cf_port;
|
||||
}
|
||||
cf_port->dma_base = (u64)devm_ioremap_nocache(&pdev->dev, res_dma->start,
|
||||
resource_size(res_dma));
|
||||
|
||||
if (!cf_port->dma_base) {
|
||||
of_node_put(dma_node);
|
||||
rv = -EINVAL;
|
||||
goto free_cf_port;
|
||||
}
|
||||
|
||||
irq_handler = octeon_cf_interrupt;
|
||||
i = platform_get_irq(dma_dev, 0);
|
||||
if (i > 0)
|
||||
irq = i;
|
||||
}
|
||||
of_node_put(dma_node);
|
||||
}
|
||||
res_cs1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
if (!res_cs1) {
|
||||
rv = -EINVAL;
|
||||
goto free_cf_port;
|
||||
}
|
||||
cs1 = devm_ioremap_nocache(&pdev->dev, res_cs1->start,
|
||||
res_cs1->end - res_cs1->start + 1);
|
||||
|
||||
if (!cs1)
|
||||
goto free_cf_port;
|
||||
|
||||
if (reg_len < (n_addr + n_size + 1) * sizeof(__be32)) {
|
||||
rv = -EINVAL;
|
||||
goto free_cf_port;
|
||||
}
|
||||
cs_num += n_addr + n_size;
|
||||
cf_port->cs1 = be32_to_cpup(cs_num);
|
||||
}
|
||||
|
||||
res_cs0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
||||
if (!res_cs0)
|
||||
return -EINVAL;
|
||||
|
||||
ocd = pdev->dev.platform_data;
|
||||
if (!res_cs0) {
|
||||
rv = -EINVAL;
|
||||
goto free_cf_port;
|
||||
}
|
||||
|
||||
cs0 = devm_ioremap_nocache(&pdev->dev, res_cs0->start,
|
||||
resource_size(res_cs0));
|
||||
|
||||
if (!cs0)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Determine from availability of DMA if True IDE mode or not */
|
||||
if (ocd->dma_engine >= 0) {
|
||||
res_cs1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
if (!res_cs1)
|
||||
return -EINVAL;
|
||||
|
||||
cs1 = devm_ioremap_nocache(&pdev->dev, res_cs1->start,
|
||||
resource_size(res_cs1));
|
||||
|
||||
if (!cs1)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
cf_port = kzalloc(sizeof(*cf_port), GFP_KERNEL);
|
||||
if (!cf_port)
|
||||
return -ENOMEM;
|
||||
goto free_cf_port;
|
||||
|
||||
/* allocate host */
|
||||
host = ata_host_alloc(&pdev->dev, 1);
|
||||
|
|
@ -846,21 +955,22 @@ static int __devinit octeon_cf_probe(struct platform_device *pdev)
|
|||
|
||||
ap = host->ports[0];
|
||||
ap->private_data = cf_port;
|
||||
pdev->dev.platform_data = cf_port;
|
||||
cf_port->ap = ap;
|
||||
ap->ops = &octeon_cf_ops;
|
||||
ap->pio_mask = ATA_PIO6;
|
||||
ap->flags |= ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING;
|
||||
|
||||
base = cs0 + ocd->base_region_bias;
|
||||
if (!ocd->is16bit) {
|
||||
if (!is_16bit) {
|
||||
base = cs0 + 0x800;
|
||||
ap->ioaddr.cmd_addr = base;
|
||||
ata_sff_std_ports(&ap->ioaddr);
|
||||
|
||||
ap->ioaddr.altstatus_addr = base + 0xe;
|
||||
ap->ioaddr.ctl_addr = base + 0xe;
|
||||
octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer8;
|
||||
} else if (cs1) {
|
||||
/* Presence of cs1 indicates True IDE mode. */
|
||||
} else if (cf_port->is_true_ide) {
|
||||
base = cs0;
|
||||
ap->ioaddr.cmd_addr = base + (ATA_REG_CMD << 1) + 1;
|
||||
ap->ioaddr.data_addr = base + (ATA_REG_DATA << 1);
|
||||
ap->ioaddr.error_addr = base + (ATA_REG_ERR << 1) + 1;
|
||||
|
|
@ -876,19 +986,15 @@ static int __devinit octeon_cf_probe(struct platform_device *pdev)
|
|||
ap->ioaddr.ctl_addr = cs1 + (6 << 1) + 1;
|
||||
octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16;
|
||||
|
||||
ap->mwdma_mask = ATA_MWDMA4;
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
irq_handler = octeon_cf_interrupt;
|
||||
|
||||
/* True IDE mode needs delayed work to poll for not-busy. */
|
||||
cf_port->wq = create_singlethread_workqueue(DRV_NAME);
|
||||
if (!cf_port->wq)
|
||||
goto free_cf_port;
|
||||
INIT_DELAYED_WORK(&cf_port->delayed_finish,
|
||||
octeon_cf_delayed_finish);
|
||||
ap->mwdma_mask = enable_dma ? ATA_MWDMA4 : 0;
|
||||
|
||||
/* True IDE mode needs a timer to poll for not-busy. */
|
||||
hrtimer_init(&cf_port->delayed_finish, CLOCK_MONOTONIC,
|
||||
HRTIMER_MODE_REL);
|
||||
cf_port->delayed_finish.function = octeon_cf_delayed_finish;
|
||||
} else {
|
||||
/* 16 bit but not True IDE */
|
||||
base = cs0 + 0x800;
|
||||
octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16;
|
||||
octeon_cf_ops.softreset = octeon_cf_softreset16;
|
||||
octeon_cf_ops.sff_check_status = octeon_cf_check_status16;
|
||||
|
|
@ -902,28 +1008,71 @@ static int __devinit octeon_cf_probe(struct platform_device *pdev)
|
|||
ap->ioaddr.ctl_addr = base + 0xe;
|
||||
ap->ioaddr.altstatus_addr = base + 0xe;
|
||||
}
|
||||
cf_port->c0 = ap->ioaddr.ctl_addr;
|
||||
|
||||
pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64);
|
||||
pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
|
||||
|
||||
ata_port_desc(ap, "cmd %p ctl %p", base, ap->ioaddr.ctl_addr);
|
||||
|
||||
|
||||
snprintf(version, sizeof(version), "%s %d bit%s",
|
||||
DRV_VERSION,
|
||||
(ocd->is16bit) ? 16 : 8,
|
||||
(cs1) ? ", True IDE" : "");
|
||||
ata_print_version_once(&pdev->dev, version);
|
||||
dev_info(&pdev->dev, "version " DRV_VERSION" %d bit%s.\n",
|
||||
is_16bit ? 16 : 8,
|
||||
cf_port->is_true_ide ? ", True IDE" : "");
|
||||
|
||||
return ata_host_activate(host, irq, irq_handler, 0, &octeon_cf_sht);
|
||||
return ata_host_activate(host, irq, irq_handler,
|
||||
IRQF_SHARED, &octeon_cf_sht);
|
||||
|
||||
free_cf_port:
|
||||
kfree(cf_port);
|
||||
return -ENOMEM;
|
||||
return rv;
|
||||
}
|
||||
|
||||
static void octeon_cf_shutdown(struct device *dev)
|
||||
{
|
||||
union cvmx_mio_boot_dma_cfgx dma_cfg;
|
||||
union cvmx_mio_boot_dma_intx dma_int;
|
||||
|
||||
struct octeon_cf_port *cf_port = dev->platform_data;
|
||||
|
||||
if (cf_port->dma_base) {
|
||||
/* Stop and clear the dma engine. */
|
||||
dma_cfg.u64 = 0;
|
||||
dma_cfg.s.size = -1;
|
||||
cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
|
||||
|
||||
/* Disable the interrupt. */
|
||||
dma_int.u64 = 0;
|
||||
cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
|
||||
|
||||
/* Clear the DMA complete status */
|
||||
dma_int.s.done = 1;
|
||||
cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
|
||||
|
||||
__raw_writeb(0, cf_port->c0);
|
||||
udelay(20);
|
||||
__raw_writeb(ATA_SRST, cf_port->c0);
|
||||
udelay(20);
|
||||
__raw_writeb(0, cf_port->c0);
|
||||
mdelay(100);
|
||||
}
|
||||
}
|
||||
|
||||
static struct of_device_id octeon_cf_match[] = {
|
||||
{
|
||||
.compatible = "cavium,ebt3000-compact-flash",
|
||||
},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, octeon_i2c_match);
|
||||
|
||||
static struct platform_driver octeon_cf_driver = {
|
||||
.probe = octeon_cf_probe,
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = octeon_cf_match,
|
||||
.shutdown = octeon_cf_shutdown
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue