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m68k/q40: Replace q40ide driver with pata_falcon and falconide
This allows m68k q40 systems to switch from the deprecated IDE subsystem to libata. Enhance the byte-swapping falconide and pata_falcon platform drivers to accept an irq resource, for use on q40. Atari ST-DMA IRQ arrangements seem to co-exist with q40 IRQ arrangements without too much mess. The new IO resources were added solely for the purpose of making request_region() reservations identical to those made by q40ide: these regions aren't used for actual IO. Cc: Michael Schmitz <schmitzmic@gmail.com> Cc: Richard Zidlicky <rz@linux-m68k.org> Reviewed-and-tested-by: Michael Schmitz <schmitzmic@gmail.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Finn Thain <fthain@linux-m68k.org> Link: https://lore.kernel.org/r/eefb7e9c2291e09fb4e065ce06bc105f05bb9e06.1623287706.git.fthain@linux-m68k.org Signed-off-by: Jens Axboe <axboe@kernel.dk>
This commit is contained in:
Finn Thain
Jens Axboe
parent
cabd10be0b
commit
44b1fbc0f5
10 changed files with 147 additions and 251 deletions
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@ -875,16 +875,8 @@ static const struct resource atari_scsi_tt_rsrc[] __initconst = {
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#define FALCON_IDE_BASE 0xfff00000
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static const struct resource atari_falconide_rsrc[] __initconst = {
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{
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.flags = IORESOURCE_MEM,
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.start = FALCON_IDE_BASE,
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.end = FALCON_IDE_BASE + 0x39,
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},
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{
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.flags = IORESOURCE_IRQ,
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.start = IRQ_MFP_FSCSI,
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.end = IRQ_MFP_FSCSI,
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},
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DEFINE_RES_MEM(FALCON_IDE_BASE, 0x38),
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DEFINE_RES_MEM(FALCON_IDE_BASE + 0x38, 2),
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};
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int __init atari_platform_init(void)
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@ -351,7 +351,6 @@ CONFIG_BLK_DEV_PLATFORM=y
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CONFIG_BLK_DEV_GAYLE=y
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CONFIG_BLK_DEV_BUDDHA=y
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CONFIG_BLK_DEV_FALCON_IDE=y
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CONFIG_BLK_DEV_Q40IDE=y
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CONFIG_RAID_ATTRS=m
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CONFIG_SCSI=y
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CONFIG_BLK_DEV_SD=y
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@ -317,7 +317,7 @@ CONFIG_DUMMY_IRQ=m
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CONFIG_IDE=y
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CONFIG_IDE_GD_ATAPI=y
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CONFIG_BLK_DEV_IDECD=y
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CONFIG_BLK_DEV_Q40IDE=y
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CONFIG_BLK_DEV_FALCON_IDE=y
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CONFIG_RAID_ATTRS=m
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CONFIG_SCSI=y
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CONFIG_BLK_DEV_SD=y
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@ -286,14 +286,39 @@ static int q40_set_rtc_pll(struct rtc_pll_info *pll)
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return -EINVAL;
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}
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static __init int q40_add_kbd_device(void)
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{
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struct platform_device *pdev;
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#define PCIDE_BASE1 0x1f0
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#define PCIDE_BASE2 0x170
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#define PCIDE_CTL 0x206
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static const struct resource q40_pata_rsrc_0[] __initconst = {
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DEFINE_RES_MEM(q40_isa_io_base + PCIDE_BASE1 * 4, 0x38),
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DEFINE_RES_MEM(q40_isa_io_base + (PCIDE_BASE1 + PCIDE_CTL) * 4, 2),
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DEFINE_RES_IO(PCIDE_BASE1, 8),
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DEFINE_RES_IO(PCIDE_BASE1 + PCIDE_CTL, 1),
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DEFINE_RES_IRQ(14),
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};
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static const struct resource q40_pata_rsrc_1[] __initconst = {
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DEFINE_RES_MEM(q40_isa_io_base + PCIDE_BASE2 * 4, 0x38),
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DEFINE_RES_MEM(q40_isa_io_base + (PCIDE_BASE2 + PCIDE_CTL) * 4, 2),
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DEFINE_RES_IO(PCIDE_BASE2, 8),
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DEFINE_RES_IO(PCIDE_BASE2 + PCIDE_CTL, 1),
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DEFINE_RES_IRQ(15),
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};
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static __init int q40_platform_init(void)
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{
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if (!MACH_IS_Q40)
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return -ENODEV;
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pdev = platform_device_register_simple("q40kbd", -1, NULL, 0);
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return PTR_ERR_OR_ZERO(pdev);
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platform_device_register_simple("q40kbd", -1, NULL, 0);
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platform_device_register_simple("atari-falcon-ide", 0, q40_pata_rsrc_0,
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ARRAY_SIZE(q40_pata_rsrc_0));
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platform_device_register_simple("atari-falcon-ide", 1, q40_pata_rsrc_1,
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ARRAY_SIZE(q40_pata_rsrc_1));
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return 0;
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}
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arch_initcall(q40_add_kbd_device);
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arch_initcall(q40_platform_init);
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@ -1015,11 +1015,11 @@ config PATA_CMD640_PCI
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If unsure, say N.
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config PATA_FALCON
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tristate "Atari Falcon PATA support"
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depends on M68K && ATARI
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tristate "Atari Falcon and Q40/Q60 PATA support"
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depends on M68K && (ATARI || Q40)
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help
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This option enables support for the on-board IDE
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interface on the Atari Falcon.
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interface on the Atari Falcon and Q40/Q60.
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If unsure, say N.
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@ -33,8 +33,6 @@
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#define DRV_NAME "pata_falcon"
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#define DRV_VERSION "0.1.0"
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#define ATA_HD_CONTROL 0x39
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static struct scsi_host_template pata_falcon_sht = {
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ATA_PIO_SHT(DRV_NAME),
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};
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@ -121,23 +119,42 @@ static struct ata_port_operations pata_falcon_ops = {
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static int __init pata_falcon_init_one(struct platform_device *pdev)
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{
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struct resource *res;
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struct resource *base_mem_res, *ctl_mem_res;
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struct resource *base_res, *ctl_res, *irq_res;
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struct ata_host *host;
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struct ata_port *ap;
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void __iomem *base;
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int irq = 0;
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dev_info(&pdev->dev, "Atari Falcon PATA controller\n");
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dev_info(&pdev->dev, "Atari Falcon and Q40/Q60 PATA controller\n");
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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if (!devm_request_mem_region(&pdev->dev, res->start,
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resource_size(res), DRV_NAME)) {
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base_res = platform_get_resource(pdev, IORESOURCE_IO, 0);
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if (base_res && !devm_request_region(&pdev->dev, base_res->start,
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resource_size(base_res), DRV_NAME)) {
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dev_err(&pdev->dev, "resources busy\n");
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return -EBUSY;
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}
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ctl_res = platform_get_resource(pdev, IORESOURCE_IO, 1);
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if (ctl_res && !devm_request_region(&pdev->dev, ctl_res->start,
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resource_size(ctl_res), DRV_NAME)) {
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dev_err(&pdev->dev, "resources busy\n");
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return -EBUSY;
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}
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base_mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!base_mem_res)
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return -ENODEV;
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if (!devm_request_mem_region(&pdev->dev, base_mem_res->start,
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resource_size(base_mem_res), DRV_NAME)) {
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dev_err(&pdev->dev, "resources busy\n");
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return -EBUSY;
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}
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ctl_mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!ctl_mem_res)
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return -ENODEV;
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/* allocate host */
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host = ata_host_alloc(&pdev->dev, 1);
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if (!host)
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@ -147,10 +164,10 @@ static int __init pata_falcon_init_one(struct platform_device *pdev)
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ap->ops = &pata_falcon_ops;
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ap->pio_mask = ATA_PIO4;
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ap->flags |= ATA_FLAG_SLAVE_POSS | ATA_FLAG_NO_IORDY;
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ap->flags |= ATA_FLAG_PIO_POLLING;
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base = (void __iomem *)res->start;
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ap->ioaddr.data_addr = base;
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base = (void __iomem *)base_mem_res->start;
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/* N.B. this assumes data_addr will be used for word-sized I/O only */
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ap->ioaddr.data_addr = base + 0 + 0 * 4;
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ap->ioaddr.error_addr = base + 1 + 1 * 4;
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ap->ioaddr.feature_addr = base + 1 + 1 * 4;
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ap->ioaddr.nsect_addr = base + 1 + 2 * 4;
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@ -161,14 +178,25 @@ static int __init pata_falcon_init_one(struct platform_device *pdev)
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ap->ioaddr.status_addr = base + 1 + 7 * 4;
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ap->ioaddr.command_addr = base + 1 + 7 * 4;
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ap->ioaddr.altstatus_addr = base + ATA_HD_CONTROL;
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ap->ioaddr.ctl_addr = base + ATA_HD_CONTROL;
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base = (void __iomem *)ctl_mem_res->start;
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ap->ioaddr.altstatus_addr = base + 1;
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ap->ioaddr.ctl_addr = base + 1;
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ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", (unsigned long)base,
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(unsigned long)base + ATA_HD_CONTROL);
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ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
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(unsigned long)base_mem_res->start,
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(unsigned long)ctl_mem_res->start);
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irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (irq_res && irq_res->start > 0) {
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irq = irq_res->start;
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} else {
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ap->flags |= ATA_FLAG_PIO_POLLING;
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ata_port_desc(ap, "no IRQ, using PIO polling");
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}
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/* activate */
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return ata_host_activate(host, 0, NULL, 0, &pata_falcon_sht);
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return ata_host_activate(host, irq, irq ? ata_sff_interrupt : NULL,
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IRQF_SHARED, &pata_falcon_sht);
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}
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static int __exit pata_falcon_remove_one(struct platform_device *pdev)
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@ -731,21 +731,13 @@ config BLK_DEV_BUDDHA
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to one of its IDE interfaces.
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config BLK_DEV_FALCON_IDE
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tristate "Falcon IDE interface support"
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depends on ATARI
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tristate "Falcon and Q40/Q60 IDE interface support"
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depends on ATARI || Q40
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help
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This is the IDE driver for the on-board IDE interface on the Atari
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Falcon. Say Y if you have a Falcon and want to use IDE devices (hard
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disks, CD-ROM drives, etc.) that are connected to the on-board IDE
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interface.
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config BLK_DEV_Q40IDE
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tristate "Q40/Q60 IDE interface support"
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depends on Q40
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help
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Enable the on-board IDE controller in the Q40/Q60. This should
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normally be on; disable it only if you are running a custom hard
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drive subsystem through an expansion card.
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Falcon and Q40/Q60. Say Y if you have such a machine and want to use
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IDE devices (hard disks, CD-ROM drives, etc.) that are connected to
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the on-board IDE interface.
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config BLK_DEV_PALMCHIP_BK3710
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tristate "Palmchip bk3710 IDE controller support"
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@ -29,7 +29,6 @@ obj-$(CONFIG_BLK_DEV_4DRIVES) += ide-4drives.o
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obj-$(CONFIG_BLK_DEV_GAYLE) += gayle.o
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obj-$(CONFIG_BLK_DEV_FALCON_IDE) += falconide.o
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obj-$(CONFIG_BLK_DEV_Q40IDE) += q40ide.o
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obj-$(CONFIG_BLK_DEV_BUDDHA) += buddha.o
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obj-$(CONFIG_BLK_DEV_AEC62XX) += aec62xx.o
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@ -25,12 +25,7 @@
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#define DRV_NAME "falconide"
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/*
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* Offsets from base address
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*/
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#define ATA_HD_CONTROL 0x39
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#ifdef CONFIG_ATARI
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/*
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* falconide_intr_lock is used to obtain access to the IDE interrupt,
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* which is shared between several drivers.
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@ -55,6 +50,7 @@ static void falconide_get_lock(irq_handler_t handler, void *data)
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falconide_intr_lock = 1;
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}
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}
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#endif
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static void falconide_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
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void *buf, unsigned int len)
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@ -98,8 +94,10 @@ static const struct ide_tp_ops falconide_tp_ops = {
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};
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static const struct ide_port_info falconide_port_info = {
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#ifdef CONFIG_ATARI
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.get_lock = falconide_get_lock,
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.release_lock = falconide_release_lock,
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#endif
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.tp_ops = &falconide_tp_ops,
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.host_flags = IDE_HFLAG_MMIO | IDE_HFLAG_SERIALIZE |
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IDE_HFLAG_NO_DMA,
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@ -107,7 +105,8 @@ static const struct ide_port_info falconide_port_info = {
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.chipset = ide_generic,
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};
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static void __init falconide_setup_ports(struct ide_hw *hw, unsigned long base)
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static void __init falconide_setup_ports(struct ide_hw *hw, unsigned long base,
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unsigned long ctl, int irq)
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{
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int i;
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@ -118,9 +117,9 @@ static void __init falconide_setup_ports(struct ide_hw *hw, unsigned long base)
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for (i = 1; i < 8; i++)
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hw->io_ports_array[i] = base + 1 + i * 4;
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hw->io_ports.ctl_addr = base + ATA_HD_CONTROL;
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hw->io_ports.ctl_addr = ctl + 1;
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hw->irq = IRQ_MFP_IDE;
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hw->irq = irq;
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}
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/*
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@ -129,37 +128,69 @@ static void __init falconide_setup_ports(struct ide_hw *hw, unsigned long base)
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static int __init falconide_init(struct platform_device *pdev)
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{
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struct resource *res;
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struct resource *base_mem_res, *ctl_mem_res;
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struct resource *base_res, *ctl_res, *irq_res;
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struct ide_host *host;
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struct ide_hw hw, *hws[] = { &hw };
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unsigned long base;
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int rc;
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int irq;
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dev_info(&pdev->dev, "Atari Falcon IDE controller\n");
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dev_info(&pdev->dev, "Atari Falcon and Q40/Q60 IDE controller\n");
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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if (!devm_request_mem_region(&pdev->dev, res->start,
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resource_size(res), DRV_NAME)) {
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base_res = platform_get_resource(pdev, IORESOURCE_IO, 0);
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if (base_res && !devm_request_region(&pdev->dev, base_res->start,
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resource_size(base_res), DRV_NAME)) {
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dev_err(&pdev->dev, "resources busy\n");
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return -EBUSY;
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}
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base = (unsigned long)res->start;
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falconide_setup_ports(&hw, base);
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host = ide_host_alloc(&falconide_port_info, hws, 1);
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if (host == NULL) {
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rc = -ENOMEM;
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goto err;
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ctl_res = platform_get_resource(pdev, IORESOURCE_IO, 0);
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if (ctl_res && !devm_request_region(&pdev->dev, ctl_res->start,
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resource_size(ctl_res), DRV_NAME)) {
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dev_err(&pdev->dev, "resources busy\n");
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return -EBUSY;
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}
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falconide_get_lock(NULL, NULL);
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base_mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!base_mem_res)
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return -ENODEV;
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if (!devm_request_mem_region(&pdev->dev, base_mem_res->start,
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resource_size(base_mem_res), DRV_NAME)) {
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dev_err(&pdev->dev, "resources busy\n");
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return -EBUSY;
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}
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ctl_mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!ctl_mem_res)
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return -ENODEV;
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if (MACH_IS_ATARI) {
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irq = IRQ_MFP_IDE;
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} else {
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irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (irq_res && irq_res->start > 0)
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irq = irq_res->start;
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else
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return -ENODEV;
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}
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falconide_setup_ports(&hw, base_mem_res->start, ctl_mem_res->start, irq);
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host = ide_host_alloc(&falconide_port_info, hws, 1);
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if (!host)
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return -ENOMEM;
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if (!MACH_IS_ATARI) {
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host->get_lock = NULL;
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host->release_lock = NULL;
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}
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if (host->get_lock)
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host->get_lock(NULL, NULL);
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rc = ide_host_register(host, &falconide_port_info, hws);
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falconide_release_lock();
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if (host->release_lock)
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host->release_lock();
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if (rc)
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goto err_free;
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@ -168,8 +199,6 @@ static int __init falconide_init(struct platform_device *pdev)
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return 0;
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err_free:
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ide_host_free(host);
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err:
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release_mem_region(res->start, resource_size(res));
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return rc;
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}
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@ -1,168 +0,0 @@
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/*
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* Q40 I/O port IDE Driver
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*
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* (c) Richard Zidlicky
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file COPYING in the main directory of this archive for
|
||||
* more details.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/blkdev.h>
|
||||
#include <linux/ide.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/ide.h>
|
||||
|
||||
/*
|
||||
* Bases of the IDE interfaces
|
||||
*/
|
||||
|
||||
#define Q40IDE_NUM_HWIFS 2
|
||||
|
||||
#define PCIDE_BASE1 0x1f0
|
||||
#define PCIDE_BASE2 0x170
|
||||
#define PCIDE_BASE3 0x1e8
|
||||
#define PCIDE_BASE4 0x168
|
||||
#define PCIDE_BASE5 0x1e0
|
||||
#define PCIDE_BASE6 0x160
|
||||
|
||||
static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
|
||||
PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4 , PCIDE_BASE5,
|
||||
PCIDE_BASE6 */
|
||||
};
|
||||
|
||||
static int q40ide_default_irq(unsigned long base)
|
||||
{
|
||||
switch (base) {
|
||||
case 0x1f0: return 14;
|
||||
case 0x170: return 15;
|
||||
case 0x1e8: return 11;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Addresses are pretranslated for Q40 ISA access.
|
||||
*/
|
||||
static void q40_ide_setup_ports(struct ide_hw *hw, unsigned long base, int irq)
|
||||
{
|
||||
memset(hw, 0, sizeof(*hw));
|
||||
/* BIG FAT WARNING:
|
||||
assumption: only DATA port is ever used in 16 bit mode */
|
||||
hw->io_ports.data_addr = Q40_ISA_IO_W(base);
|
||||
hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1);
|
||||
hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2);
|
||||
hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3);
|
||||
hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4);
|
||||
hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5);
|
||||
hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6);
|
||||
hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7);
|
||||
hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206);
|
||||
|
||||
hw->irq = irq;
|
||||
}
|
||||
|
||||
static void q40ide_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
|
||||
void *buf, unsigned int len)
|
||||
{
|
||||
unsigned long data_addr = drive->hwif->io_ports.data_addr;
|
||||
|
||||
if (drive->media == ide_disk && cmd && (cmd->tf_flags & IDE_TFLAG_FS)) {
|
||||
__ide_mm_insw(data_addr, buf, (len + 1) / 2);
|
||||
return;
|
||||
}
|
||||
|
||||
raw_insw_swapw((u16 *)data_addr, buf, (len + 1) / 2);
|
||||
}
|
||||
|
||||
static void q40ide_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
|
||||
void *buf, unsigned int len)
|
||||
{
|
||||
unsigned long data_addr = drive->hwif->io_ports.data_addr;
|
||||
|
||||
if (drive->media == ide_disk && cmd && (cmd->tf_flags & IDE_TFLAG_FS)) {
|
||||
__ide_mm_outsw(data_addr, buf, (len + 1) / 2);
|
||||
return;
|
||||
}
|
||||
|
||||
raw_outsw_swapw((u16 *)data_addr, buf, (len + 1) / 2);
|
||||
}
|
||||
|
||||
/* Q40 has a byte-swapped IDE interface */
|
||||
static const struct ide_tp_ops q40ide_tp_ops = {
|
||||
.exec_command = ide_exec_command,
|
||||
.read_status = ide_read_status,
|
||||
.read_altstatus = ide_read_altstatus,
|
||||
.write_devctl = ide_write_devctl,
|
||||
|
||||
.dev_select = ide_dev_select,
|
||||
.tf_load = ide_tf_load,
|
||||
.tf_read = ide_tf_read,
|
||||
|
||||
.input_data = q40ide_input_data,
|
||||
.output_data = q40ide_output_data,
|
||||
};
|
||||
|
||||
static const struct ide_port_info q40ide_port_info = {
|
||||
.tp_ops = &q40ide_tp_ops,
|
||||
.host_flags = IDE_HFLAG_MMIO | IDE_HFLAG_NO_DMA,
|
||||
.irq_flags = IRQF_SHARED,
|
||||
.chipset = ide_generic,
|
||||
};
|
||||
|
||||
/*
|
||||
* the static array is needed to have the name reported in /proc/ioports,
|
||||
* hwif->name unfortunately isn't available yet
|
||||
*/
|
||||
static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
|
||||
"ide0", "ide1"
|
||||
};
|
||||
|
||||
/*
|
||||
* Probe for Q40 IDE interfaces
|
||||
*/
|
||||
|
||||
static int __init q40ide_init(void)
|
||||
{
|
||||
int i;
|
||||
struct ide_hw hw[Q40IDE_NUM_HWIFS], *hws[] = { NULL, NULL };
|
||||
|
||||
if (!MACH_IS_Q40)
|
||||
return -ENODEV;
|
||||
|
||||
printk(KERN_INFO "ide: Q40 IDE controller\n");
|
||||
|
||||
for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
|
||||
const char *name = q40_ide_names[i];
|
||||
|
||||
if (!request_region(pcide_bases[i], 8, name)) {
|
||||
printk("could not reserve ports %lx-%lx for %s\n",
|
||||
pcide_bases[i],pcide_bases[i]+8,name);
|
||||
continue;
|
||||
}
|
||||
if (!request_region(pcide_bases[i]+0x206, 1, name)) {
|
||||
printk("could not reserve port %lx for %s\n",
|
||||
pcide_bases[i]+0x206,name);
|
||||
release_region(pcide_bases[i], 8);
|
||||
continue;
|
||||
}
|
||||
q40_ide_setup_ports(&hw[i], pcide_bases[i],
|
||||
q40ide_default_irq(pcide_bases[i]));
|
||||
|
||||
hws[i] = &hw[i];
|
||||
}
|
||||
|
||||
return ide_host_add(&q40ide_port_info, hws, Q40IDE_NUM_HWIFS, NULL);
|
||||
}
|
||||
|
||||
module_init(q40ide_init);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in a new issue