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arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes
Add pcie dtsi nodes for two controllers found on sa8775p platform. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Link: https://lore.kernel.org/r/1689960276-29266-4-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Mrinmay Sarkar
Bjorn Andersson
parent
74cf6675c3
commit
489f14be0e
1 changed files with 202 additions and 2 deletions
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@ -481,8 +481,8 @@ gcc: clock-controller@100000 {
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<0>,
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<0>,
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<0>,
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<0>,
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<0>,
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<&pcie0_phy>,
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<&pcie1_phy>,
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<0>,
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<0>,
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<0>;
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@ -2357,4 +2357,204 @@ arch_timer: timer {
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pcie0: pci@1c00000{
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compatible = "qcom,pcie-sa8775p";
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reg = <0x0 0x01c00000 0x0 0x3000>,
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<0x0 0x40000000 0x0 0xf20>,
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<0x0 0x40000f20 0x0 0xa8>,
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<0x0 0x40001000 0x0 0x4000>,
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<0x0 0x40100000 0x0 0x100000>,
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<0x0 0x01c03000 0x0 0x1000>;
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reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
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bus-range = <0x00 0xff>;
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dma-coherent;
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linux,pci-domain = <0>;
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num-lanes = <2>;
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interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0", "msi1", "msi2", "msi3",
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"msi4", "msi5", "msi6", "msi7";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
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clock-names = "aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a";
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assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
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assigned-clock-rates = <19200000>;
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interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
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<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
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<0x100 &pcie_smmu 0x0001 0x1>;
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resets = <&gcc GCC_PCIE_0_BCR>;
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reset-names = "pci";
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power-domains = <&gcc PCIE_0_GDSC>;
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phys = <&pcie0_phy>;
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phy-names = "pciephy";
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status = "disabled";
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};
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pcie0_phy: phy@1c04000 {
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compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
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reg = <0x0 0x1c04000 0x0 0x2000>;
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clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_CLKREF_EN>,
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<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
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<&gcc GCC_PCIE_0_PIPE_CLK>,
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<&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
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<&gcc GCC_PCIE_0_PHY_AUX_CLK>;
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clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
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"pipediv2", "phy_aux";
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assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
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assigned-clock-rates = <100000000>;
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resets = <&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "phy";
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#clock-cells = <0>;
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clock-output-names = "pcie_0_pipe_clk";
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#phy-cells = <0>;
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status = "disabled";
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};
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pcie1: pci@1c10000{
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compatible = "qcom,pcie-sa8775p";
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reg = <0x0 0x01c10000 0x0 0x3000>,
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<0x0 0x60000000 0x0 0xf20>,
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<0x0 0x60000f20 0x0 0xa8>,
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<0x0 0x60001000 0x0 0x4000>,
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<0x0 0x60100000 0x0 0x100000>,
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<0x0 0x01c13000 0x0 0x1000>;
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reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
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<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
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bus-range = <0x00 0xff>;
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dma-coherent;
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linux,pci-domain = <1>;
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num-lanes = <4>;
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interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0", "msi1", "msi2", "msi3",
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"msi4", "msi5", "msi6", "msi7";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
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<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
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clock-names = "aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a";
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assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
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assigned-clock-rates = <19200000>;
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interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
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<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
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<0x100 &pcie_smmu 0x0081 0x1>;
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resets = <&gcc GCC_PCIE_1_BCR>;
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reset-names = "pci";
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power-domains = <&gcc PCIE_1_GDSC>;
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phys = <&pcie1_phy>;
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phy-names = "pciephy";
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status = "disabled";
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};
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pcie1_phy: phy@1c14000 {
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compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
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reg = <0x0 0x1c14000 0x0 0x4000>;
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clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
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<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_CLKREF_EN>,
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<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
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<&gcc GCC_PCIE_1_PIPE_CLK>,
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<&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
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<&gcc GCC_PCIE_1_PHY_AUX_CLK>;
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clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
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"pipediv2", "phy_aux";
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assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
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assigned-clock-rates = <100000000>;
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resets = <&gcc GCC_PCIE_1_PHY_BCR>;
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reset-names = "phy";
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#clock-cells = <0>;
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clock-output-names = "pcie_1_pipe_clk";
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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