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KVM: X86: Provide a capability to disable MWAIT intercepts
Allowing a guest to execute MWAIT without interception enables a guest to put a (physical) CPU into a power saving state, where it takes longer to return from than what may be desired by the host. Don't give a guest that power over a host by default. (Especially, since nothing prevents a guest from using MWAIT even when it is not advertised via CPUID.) Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Jan H. Schönherr <jschoenh@amazon.de> Signed-off-by: Wanpeng Li <wanpengli@tencent.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Wanpeng Li
Paolo Bonzini
parent
4956aa3b8b
commit
4d5422cea3
8 changed files with 53 additions and 25 deletions
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@ -4358,6 +4358,24 @@ enables QEMU to build error log and branch to guest kernel registered
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machine check handling routine. Without this capability KVM will
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branch to guests' 0x200 interrupt vector.
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7.13 KVM_CAP_X86_DISABLE_EXITS
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Architectures: x86
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Parameters: args[0] defines which exits are disabled
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Returns: 0 on success, -EINVAL when args[0] contains invalid exits
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Valid bits in args[0] are
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#define KVM_X86_DISABLE_EXITS_MWAIT (1 << 0)
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Enabling this capability on a VM provides userspace with a way to no
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longer intercept some instructions for improved latency in some
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workloads, and is suggested when vCPUs are associated to dedicated
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physical CPUs. More bits can be added in the future; userspace can
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just pass the KVM_CHECK_EXTENSION result to KVM_ENABLE_CAP to disable
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all such vmexits.
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8. Other capabilities.
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----------------------
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@ -4470,15 +4488,6 @@ reserved.
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Both registers and addresses are 64-bits wide.
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It will be possible to run 64-bit or 32-bit guest code.
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8.8 KVM_CAP_X86_GUEST_MWAIT
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Architectures: x86
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This capability indicates that guest using memory monotoring instructions
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(MWAIT/MWAITX) to stop the virtual CPU will not cause a VM exit. As such time
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spent while virtual CPU is halted in this way will then be accounted for as
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guest running time on the host (as opposed to e.g. HLT).
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8.9 KVM_CAP_ARM_USER_IRQ
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Architectures: arm, arm64
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@ -811,6 +811,8 @@ struct kvm_arch {
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gpa_t wall_clock;
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bool mwait_in_guest;
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bool ept_identity_pagetable_done;
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gpa_t ept_identity_map_addr;
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@ -1398,7 +1398,7 @@ static void init_vmcb(struct vcpu_svm *svm)
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set_intercept(svm, INTERCEPT_XSETBV);
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set_intercept(svm, INTERCEPT_RSM);
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if (!kvm_mwait_in_guest()) {
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if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
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set_intercept(svm, INTERCEPT_MONITOR);
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set_intercept(svm, INTERCEPT_MWAIT);
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}
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@ -3746,13 +3746,11 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
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CPU_BASED_UNCOND_IO_EXITING |
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CPU_BASED_MOV_DR_EXITING |
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CPU_BASED_USE_TSC_OFFSETING |
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CPU_BASED_MWAIT_EXITING |
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CPU_BASED_MONITOR_EXITING |
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CPU_BASED_INVLPG_EXITING |
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CPU_BASED_RDPMC_EXITING;
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if (!kvm_mwait_in_guest())
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min |= CPU_BASED_MWAIT_EXITING |
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CPU_BASED_MONITOR_EXITING;
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opt = CPU_BASED_TPR_SHADOW |
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CPU_BASED_USE_MSR_BITMAPS |
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CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
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@ -5544,6 +5542,9 @@ static u32 vmx_exec_control(struct vcpu_vmx *vmx)
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exec_control |= CPU_BASED_CR3_STORE_EXITING |
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CPU_BASED_CR3_LOAD_EXITING |
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CPU_BASED_INVLPG_EXITING;
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if (kvm_mwait_in_guest(vmx->vcpu.kvm))
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exec_control &= ~(CPU_BASED_MWAIT_EXITING |
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CPU_BASED_MONITOR_EXITING);
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return exec_control;
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}
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@ -2813,9 +2813,15 @@ static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
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return r;
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}
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static inline bool kvm_can_mwait_in_guest(void)
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{
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return boot_cpu_has(X86_FEATURE_MWAIT) &&
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!boot_cpu_has_bug(X86_BUG_MONITOR);
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}
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int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
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{
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int r;
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int r = 0;
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switch (ext) {
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case KVM_CAP_IRQCHIP:
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@ -2871,8 +2877,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
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case KVM_CAP_ADJUST_CLOCK:
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r = KVM_CLOCK_TSC_STABLE;
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break;
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case KVM_CAP_X86_GUEST_MWAIT:
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r = kvm_mwait_in_guest();
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case KVM_CAP_X86_DISABLE_EXITS:
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if(kvm_can_mwait_in_guest())
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r |= KVM_X86_DISABLE_EXITS_MWAIT;
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break;
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case KVM_CAP_X86_SMM:
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/* SMBASE is usually relocated above 1M on modern chipsets,
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@ -2913,7 +2920,6 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
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r = KVM_X2APIC_API_VALID_FLAGS;
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break;
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default:
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r = 0;
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break;
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}
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return r;
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@ -4218,6 +4224,16 @@ static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
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r = 0;
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break;
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case KVM_CAP_X86_DISABLE_EXITS:
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r = -EINVAL;
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if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
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break;
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if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
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kvm_can_mwait_in_guest())
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kvm->arch.mwait_in_guest = true;
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r = 0;
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break;
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default:
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r = -EINVAL;
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break;
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@ -2,8 +2,6 @@
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#ifndef ARCH_X86_KVM_X86_H
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#define ARCH_X86_KVM_X86_H
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#include <asm/processor.h>
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#include <asm/mwait.h>
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#include <linux/kvm_host.h>
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#include <asm/pvclock.h>
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#include "kvm_cache_regs.h"
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@ -266,10 +264,12 @@ static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
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__rem; \
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})
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static inline bool kvm_mwait_in_guest(void)
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#define KVM_X86_DISABLE_EXITS_MWAIT (1 << 0)
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#define KVM_X86_DISABLE_VALID_EXITS (KVM_X86_DISABLE_EXITS_MWAIT)
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static inline bool kvm_mwait_in_guest(struct kvm *kvm)
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{
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return boot_cpu_has(X86_FEATURE_MWAIT) &&
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!boot_cpu_has_bug(X86_BUG_MONITOR);
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return kvm->arch.mwait_in_guest;
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}
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#endif
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@ -929,7 +929,7 @@ struct kvm_ppc_resize_hpt {
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#define KVM_CAP_S390_GS 140
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#define KVM_CAP_S390_AIS 141
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#define KVM_CAP_SPAPR_TCE_VFIO 142
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#define KVM_CAP_X86_GUEST_MWAIT 143
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#define KVM_CAP_X86_DISABLE_EXITS 143
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#define KVM_CAP_ARM_USER_IRQ 144
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#define KVM_CAP_S390_CMMA_MIGRATION 145
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#define KVM_CAP_PPC_FWNMI 146
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@ -924,7 +924,7 @@ struct kvm_ppc_resize_hpt {
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#define KVM_CAP_S390_GS 140
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#define KVM_CAP_S390_AIS 141
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#define KVM_CAP_SPAPR_TCE_VFIO 142
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#define KVM_CAP_X86_GUEST_MWAIT 143
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#define KVM_CAP_X86_DISABLE_EXITS 143
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#define KVM_CAP_ARM_USER_IRQ 144
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#define KVM_CAP_S390_CMMA_MIGRATION 145
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#define KVM_CAP_PPC_FWNMI 146
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