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dt-bindings: net: dp83869: Add TI dp83869 phy
Add dt bindings for the TI dp83869 Gigabit ethernet phy device. Signed-off-by: Dan Murphy <dmurphy@ti.com> CC: Rob Herring <robh+dt@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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Dan Murphy
David S. Miller
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2 changed files with 126 additions and 0 deletions
84
Documentation/devicetree/bindings/net/ti,dp83869.yaml
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Documentation/devicetree/bindings/net/ti,dp83869.yaml
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# SPDX-License-Identifier: GPL-2.0
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# Copyright (C) 2019 Texas Instruments Incorporated
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/net/ti,dp83869.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: TI DP83869 ethernet PHY
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allOf:
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- $ref: "ethernet-controller.yaml#"
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maintainers:
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- Dan Murphy <dmurphy@ti.com>
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description: |
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The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
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with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
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1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
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100BASE-FX Fiber protocols.
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This device interfaces to the MAC layer through Reduced GMII (RGMII) and
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SGMII The DP83869HM supports Media Conversion in Managed mode. In this mode,
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the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
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conversions. The DP83869HM can also support Bridge Conversion from RGMII to
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SGMII and SGMII to RGMII.
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Specifications about the charger can be found at:
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http://www.ti.com/lit/ds/symlink/dp83869hm.pdf
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properties:
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reg:
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maxItems: 1
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ti,min-output-impedance:
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type: boolean
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description: |
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MAC Interface Impedance control to set the programmable output impedance
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to a minimum value (35 ohms).
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ti,max-output-impedance:
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type: boolean
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description: |
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MAC Interface Impedance control to set the programmable output impedance
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to a maximum value (70 ohms).
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tx-fifo-depth:
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$ref: /schemas/types.yaml#definitions/uint32
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description: |
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Transmitt FIFO depth see dt-bindings/net/ti-dp83869.h for values
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rx-fifo-depth:
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$ref: /schemas/types.yaml#definitions/uint32
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description: |
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Receive FIFO depth see dt-bindings/net/ti-dp83869.h for values
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ti,clk-output-sel:
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$ref: /schemas/types.yaml#definitions/uint32
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description: |
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Muxing option for CLK_OUT pin see dt-bindings/net/ti-dp83869.h for values.
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ti,op-mode:
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$ref: /schemas/types.yaml#definitions/uint32
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description: |
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Operational mode for the PHY. If this is not set then the operational
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mode is set by the straps. see dt-bindings/net/ti-dp83869.h for values
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required:
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- reg
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examples:
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- |
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#include <dt-bindings/net/ti-dp83869.h>
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mdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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tx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
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rx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
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ti,max-output-impedance = "true";
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ti,clk-output-sel = <DP83869_CLK_O_SEL_CHN_A_RCLK>;
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};
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};
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include/dt-bindings/net/ti-dp83869.h
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include/dt-bindings/net/ti-dp83869.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Device Tree constants for the Texas Instruments DP83869 PHY
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*
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* Author: Dan Murphy <dmurphy@ti.com>
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*
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* Copyright: (C) 2019 Texas Instruments, Inc.
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*/
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#ifndef _DT_BINDINGS_TI_DP83869_H
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#define _DT_BINDINGS_TI_DP83869_H
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/* PHY CTRL bits */
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#define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB 0x00
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#define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB 0x01
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#define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02
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#define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
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/* IO_MUX_CFG - Clock output selection */
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#define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0
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#define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1
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#define DP83869_CLK_O_SEL_CHN_C_RCLK 0x2
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#define DP83869_CLK_O_SEL_CHN_D_RCLK 0x3
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#define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4
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#define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5
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#define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6
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#define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7
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#define DP83869_CLK_O_SEL_CHN_A_TCLK 0x8
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#define DP83869_CLK_O_SEL_CHN_B_TCLK 0x9
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#define DP83869_CLK_O_SEL_CHN_C_TCLK 0xa
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#define DP83869_CLK_O_SEL_CHN_D_TCLK 0xb
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#define DP83869_CLK_O_SEL_REF_CLK 0xc
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#define DP83869_RGMII_COPPER_ETHERNET 0x00
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#define DP83869_RGMII_1000_BASE 0x01
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#define DP83869_RGMII_100_BASE 0x02
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#define DP83869_RGMII_SGMII_BRIDGE 0x03
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#define DP83869_1000M_MEDIA_CONVERT 0x04
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#define DP83869_100M_MEDIA_CONVERT 0x05
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#define DP83869_SGMII_COPPER_ETHERNET 0x06
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#endif
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