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drm/radeon/kms: remove r6xx+ blit copy routines
No longer used now that we use the async dma engines or CP DMA for bo copies. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
8dddb993bc
commit
4f86296758
14 changed files with 33 additions and 1764 deletions
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@ -72,8 +72,8 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
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radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \
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rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \
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r200.o radeon_legacy_tv.o r600_cs.o r600_blit_shaders.o \
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r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \
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evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \
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radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \
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evergreen.o evergreen_cs.o evergreen_blit_shaders.o \
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evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \
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atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
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si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \
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@ -317,58 +317,4 @@ const u32 cayman_default_state[] =
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0x00000010, /* */
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};
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const u32 cayman_vs[] =
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{
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0x00000004,
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0x80400400,
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0x0000a03c,
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0x95000688,
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0x00004000,
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0x15000688,
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0x00000000,
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0x88000000,
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0x04000000,
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0x67961001,
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#ifdef __BIG_ENDIAN
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0x00020000,
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#else
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0x00000000,
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#endif
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0x00000000,
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0x04000000,
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0x67961000,
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#ifdef __BIG_ENDIAN
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0x00020008,
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#else
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0x00000008,
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#endif
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0x00000000,
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};
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const u32 cayman_ps[] =
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{
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0x00000004,
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0xa00c0000,
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0x00000008,
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0x80400000,
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0x00000000,
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0x95000688,
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0x00000000,
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0x88000000,
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0x00380400,
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0x00146b10,
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0x00380000,
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0x20146b10,
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0x00380400,
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0x40146b00,
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0x80380000,
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0x60146b00,
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0x00000010,
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0x000d1000,
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0xb0800000,
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0x00000000,
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};
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const u32 cayman_ps_size = ARRAY_SIZE(cayman_ps);
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const u32 cayman_vs_size = ARRAY_SIZE(cayman_vs);
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const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state);
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@ -5144,13 +5144,6 @@ static int evergreen_startup(struct radeon_device *rdev)
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}
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evergreen_gpu_init(rdev);
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r = evergreen_blit_init(rdev);
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if (r) {
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r600_blit_fini(rdev);
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rdev->asic->copy.copy = NULL;
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dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
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}
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/* allocate rlc buffers */
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if (rdev->flags & RADEON_IS_IGP) {
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rdev->rlc.reg_list = sumo_rlc_save_restore_register_list;
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@ -5420,7 +5413,6 @@ int evergreen_init(struct radeon_device *rdev)
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void evergreen_fini(struct radeon_device *rdev)
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{
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r600_audio_fini(rdev);
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r600_blit_fini(rdev);
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r700_cp_fini(rdev);
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r600_dma_fini(rdev);
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r600_irq_fini(rdev);
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@ -1,729 +0,0 @@
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/*
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* Copyright 2010 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Alex Deucher <alexander.deucher@amd.com>
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*/
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon.h"
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#include "evergreend.h"
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#include "evergreen_blit_shaders.h"
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#include "cayman_blit_shaders.h"
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#include "radeon_blit_common.h"
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/* emits 17 */
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static void
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set_render_target(struct radeon_device *rdev, int format,
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int w, int h, u64 gpu_addr)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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u32 cb_color_info;
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int pitch, slice;
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h = ALIGN(h, 8);
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if (h < 8)
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h = 8;
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cb_color_info = CB_FORMAT(format) |
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CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
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CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
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pitch = (w / 8) - 1;
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slice = ((w * h) / 64) - 1;
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 15));
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radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);
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radeon_ring_write(ring, gpu_addr >> 8);
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radeon_ring_write(ring, pitch);
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radeon_ring_write(ring, slice);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, cb_color_info);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, (w - 1) | ((h - 1) << 16));
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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}
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/* emits 5dw */
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static void
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cp_set_surface_sync(struct radeon_device *rdev,
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u32 sync_type, u32 size,
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u64 mc_addr)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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u32 cp_coher_size;
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if (size == 0xffffffff)
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cp_coher_size = 0xffffffff;
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else
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cp_coher_size = ((size + 255) >> 8);
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if (rdev->family >= CHIP_CAYMAN) {
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/* CP_COHER_CNTL2 has to be set manually when submitting a surface_sync
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* to the RB directly. For IBs, the CP programs this as part of the
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* surface_sync packet.
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*/
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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radeon_ring_write(ring, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2);
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radeon_ring_write(ring, 0); /* CP_COHER_CNTL2 */
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}
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radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
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radeon_ring_write(ring, sync_type);
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radeon_ring_write(ring, cp_coher_size);
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radeon_ring_write(ring, mc_addr >> 8);
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radeon_ring_write(ring, 10); /* poll interval */
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}
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/* emits 11dw + 1 surface sync = 16dw */
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static void
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set_shaders(struct radeon_device *rdev)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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u64 gpu_addr;
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/* VS */
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gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 3));
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radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2);
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radeon_ring_write(ring, gpu_addr >> 8);
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radeon_ring_write(ring, 2);
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radeon_ring_write(ring, 0);
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/* PS */
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gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 4));
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radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2);
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radeon_ring_write(ring, gpu_addr >> 8);
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radeon_ring_write(ring, 1);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 2);
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gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
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cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
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}
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/* emits 10 + 1 sync (5) = 15 */
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static void
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set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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u32 sq_vtx_constant_word2, sq_vtx_constant_word3;
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/* high addr, stride */
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sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
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SQ_VTXC_STRIDE(16);
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#ifdef __BIG_ENDIAN
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sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
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#endif
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/* xyzw swizzles */
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sq_vtx_constant_word3 = SQ_VTCX_SEL_X(SQ_SEL_X) |
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SQ_VTCX_SEL_Y(SQ_SEL_Y) |
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SQ_VTCX_SEL_Z(SQ_SEL_Z) |
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SQ_VTCX_SEL_W(SQ_SEL_W);
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radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8));
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radeon_ring_write(ring, 0x580);
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radeon_ring_write(ring, gpu_addr & 0xffffffff);
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radeon_ring_write(ring, 48 - 1); /* size */
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radeon_ring_write(ring, sq_vtx_constant_word2);
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radeon_ring_write(ring, sq_vtx_constant_word3);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER));
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if ((rdev->family == CHIP_CEDAR) ||
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(rdev->family == CHIP_PALM) ||
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(rdev->family == CHIP_SUMO) ||
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(rdev->family == CHIP_SUMO2) ||
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(rdev->family == CHIP_CAICOS))
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cp_set_surface_sync(rdev,
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PACKET3_TC_ACTION_ENA, 48, gpu_addr);
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else
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cp_set_surface_sync(rdev,
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PACKET3_VC_ACTION_ENA, 48, gpu_addr);
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}
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/* emits 10 */
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static void
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set_tex_resource(struct radeon_device *rdev,
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int format, int w, int h, int pitch,
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u64 gpu_addr, u32 size)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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u32 sq_tex_resource_word0, sq_tex_resource_word1;
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u32 sq_tex_resource_word4, sq_tex_resource_word7;
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if (h < 1)
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h = 1;
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sq_tex_resource_word0 = TEX_DIM(SQ_TEX_DIM_2D);
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sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) |
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((w - 1) << 18));
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sq_tex_resource_word1 = ((h - 1) << 0) |
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TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
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/* xyzw swizzles */
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sq_tex_resource_word4 = TEX_DST_SEL_X(SQ_SEL_X) |
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TEX_DST_SEL_Y(SQ_SEL_Y) |
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TEX_DST_SEL_Z(SQ_SEL_Z) |
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TEX_DST_SEL_W(SQ_SEL_W);
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sq_tex_resource_word7 = format |
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S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_TEXTURE);
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cp_set_surface_sync(rdev,
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PACKET3_TC_ACTION_ENA, size, gpu_addr);
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radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8));
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, sq_tex_resource_word0);
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radeon_ring_write(ring, sq_tex_resource_word1);
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radeon_ring_write(ring, gpu_addr >> 8);
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radeon_ring_write(ring, gpu_addr >> 8);
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radeon_ring_write(ring, sq_tex_resource_word4);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, sq_tex_resource_word7);
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}
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/* emits 12 */
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static void
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set_scissors(struct radeon_device *rdev, int x1, int y1,
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int x2, int y2)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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/* workaround some hw bugs */
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if (x2 == 0)
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x1 = 1;
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if (y2 == 0)
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y1 = 1;
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if (rdev->family >= CHIP_CAYMAN) {
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if ((x2 == 1) && (y2 == 1))
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x2 = 2;
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}
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
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radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
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radeon_ring_write(ring, (x1 << 0) | (y1 << 16));
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radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
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radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
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radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
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radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
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radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
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radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
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radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
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}
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/* emits 10 */
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static void
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draw_auto(struct radeon_device *rdev)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);
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radeon_ring_write(ring, DI_PT_RECTLIST);
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radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));
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radeon_ring_write(ring,
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#ifdef __BIG_ENDIAN
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(2 << 2) |
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#endif
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DI_INDEX_SIZE_16_BIT);
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radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));
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radeon_ring_write(ring, 1);
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radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
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radeon_ring_write(ring, 3);
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radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);
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}
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/* emits 39 */
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static void
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set_default_state(struct radeon_device *rdev)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3;
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u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2;
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u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3;
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int num_ps_gprs, num_vs_gprs, num_temp_gprs;
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int num_gs_gprs, num_es_gprs, num_hs_gprs, num_ls_gprs;
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int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
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int num_hs_threads, num_ls_threads;
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int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
|
||||
int num_hs_stack_entries, num_ls_stack_entries;
|
||||
u64 gpu_addr;
|
||||
int dwords;
|
||||
|
||||
/* set clear context state */
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
|
||||
radeon_ring_write(ring, 0);
|
||||
|
||||
if (rdev->family < CHIP_CAYMAN) {
|
||||
switch (rdev->family) {
|
||||
case CHIP_CEDAR:
|
||||
default:
|
||||
num_ps_gprs = 93;
|
||||
num_vs_gprs = 46;
|
||||
num_temp_gprs = 4;
|
||||
num_gs_gprs = 31;
|
||||
num_es_gprs = 31;
|
||||
num_hs_gprs = 23;
|
||||
num_ls_gprs = 23;
|
||||
num_ps_threads = 96;
|
||||
num_vs_threads = 16;
|
||||
num_gs_threads = 16;
|
||||
num_es_threads = 16;
|
||||
num_hs_threads = 16;
|
||||
num_ls_threads = 16;
|
||||
num_ps_stack_entries = 42;
|
||||
num_vs_stack_entries = 42;
|
||||
num_gs_stack_entries = 42;
|
||||
num_es_stack_entries = 42;
|
||||
num_hs_stack_entries = 42;
|
||||
num_ls_stack_entries = 42;
|
||||
break;
|
||||
case CHIP_REDWOOD:
|
||||
num_ps_gprs = 93;
|
||||
num_vs_gprs = 46;
|
||||
num_temp_gprs = 4;
|
||||
num_gs_gprs = 31;
|
||||
num_es_gprs = 31;
|
||||
num_hs_gprs = 23;
|
||||
num_ls_gprs = 23;
|
||||
num_ps_threads = 128;
|
||||
num_vs_threads = 20;
|
||||
num_gs_threads = 20;
|
||||
num_es_threads = 20;
|
||||
num_hs_threads = 20;
|
||||
num_ls_threads = 20;
|
||||
num_ps_stack_entries = 42;
|
||||
num_vs_stack_entries = 42;
|
||||
num_gs_stack_entries = 42;
|
||||
num_es_stack_entries = 42;
|
||||
num_hs_stack_entries = 42;
|
||||
num_ls_stack_entries = 42;
|
||||
break;
|
||||
case CHIP_JUNIPER:
|
||||
num_ps_gprs = 93;
|
||||
num_vs_gprs = 46;
|
||||
num_temp_gprs = 4;
|
||||
num_gs_gprs = 31;
|
||||
num_es_gprs = 31;
|
||||
num_hs_gprs = 23;
|
||||
num_ls_gprs = 23;
|
||||
num_ps_threads = 128;
|
||||
num_vs_threads = 20;
|
||||
num_gs_threads = 20;
|
||||
num_es_threads = 20;
|
||||
num_hs_threads = 20;
|
||||
num_ls_threads = 20;
|
||||
num_ps_stack_entries = 85;
|
||||
num_vs_stack_entries = 85;
|
||||
num_gs_stack_entries = 85;
|
||||
num_es_stack_entries = 85;
|
||||
num_hs_stack_entries = 85;
|
||||
num_ls_stack_entries = 85;
|
||||
break;
|
||||
case CHIP_CYPRESS:
|
||||
case CHIP_HEMLOCK:
|
||||
num_ps_gprs = 93;
|
||||
num_vs_gprs = 46;
|
||||
num_temp_gprs = 4;
|
||||
num_gs_gprs = 31;
|
||||
num_es_gprs = 31;
|
||||
num_hs_gprs = 23;
|
||||
num_ls_gprs = 23;
|
||||
num_ps_threads = 128;
|
||||
num_vs_threads = 20;
|
||||
num_gs_threads = 20;
|
||||
num_es_threads = 20;
|
||||
num_hs_threads = 20;
|
||||
num_ls_threads = 20;
|
||||
num_ps_stack_entries = 85;
|
||||
num_vs_stack_entries = 85;
|
||||
num_gs_stack_entries = 85;
|
||||
num_es_stack_entries = 85;
|
||||
num_hs_stack_entries = 85;
|
||||
num_ls_stack_entries = 85;
|
||||
break;
|
||||
case CHIP_PALM:
|
||||
num_ps_gprs = 93;
|
||||
num_vs_gprs = 46;
|
||||
num_temp_gprs = 4;
|
||||
num_gs_gprs = 31;
|
||||
num_es_gprs = 31;
|
||||
num_hs_gprs = 23;
|
||||
num_ls_gprs = 23;
|
||||
num_ps_threads = 96;
|
||||
num_vs_threads = 16;
|
||||
num_gs_threads = 16;
|
||||
num_es_threads = 16;
|
||||
num_hs_threads = 16;
|
||||
num_ls_threads = 16;
|
||||
num_ps_stack_entries = 42;
|
||||
num_vs_stack_entries = 42;
|
||||
num_gs_stack_entries = 42;
|
||||
num_es_stack_entries = 42;
|
||||
num_hs_stack_entries = 42;
|
||||
num_ls_stack_entries = 42;
|
||||
break;
|
||||
case CHIP_SUMO:
|
||||
num_ps_gprs = 93;
|
||||
num_vs_gprs = 46;
|
||||
num_temp_gprs = 4;
|
||||
num_gs_gprs = 31;
|
||||
num_es_gprs = 31;
|
||||
num_hs_gprs = 23;
|
||||
num_ls_gprs = 23;
|
||||
num_ps_threads = 96;
|
||||
num_vs_threads = 25;
|
||||
num_gs_threads = 25;
|
||||
num_es_threads = 25;
|
||||
num_hs_threads = 25;
|
||||
num_ls_threads = 25;
|
||||
num_ps_stack_entries = 42;
|
||||
num_vs_stack_entries = 42;
|
||||
num_gs_stack_entries = 42;
|
||||
num_es_stack_entries = 42;
|
||||
num_hs_stack_entries = 42;
|
||||
num_ls_stack_entries = 42;
|
||||
break;
|
||||
case CHIP_SUMO2:
|
||||
num_ps_gprs = 93;
|
||||
num_vs_gprs = 46;
|
||||
num_temp_gprs = 4;
|
||||
num_gs_gprs = 31;
|
||||
num_es_gprs = 31;
|
||||
num_hs_gprs = 23;
|
||||
num_ls_gprs = 23;
|
||||
num_ps_threads = 96;
|
||||
num_vs_threads = 25;
|
||||
num_gs_threads = 25;
|
||||
num_es_threads = 25;
|
||||
num_hs_threads = 25;
|
||||
num_ls_threads = 25;
|
||||
num_ps_stack_entries = 85;
|
||||
num_vs_stack_entries = 85;
|
||||
num_gs_stack_entries = 85;
|
||||
num_es_stack_entries = 85;
|
||||
num_hs_stack_entries = 85;
|
||||
num_ls_stack_entries = 85;
|
||||
break;
|
||||
case CHIP_BARTS:
|
||||
num_ps_gprs = 93;
|
||||
num_vs_gprs = 46;
|
||||
num_temp_gprs = 4;
|
||||
num_gs_gprs = 31;
|
||||
num_es_gprs = 31;
|
||||
num_hs_gprs = 23;
|
||||
num_ls_gprs = 23;
|
||||
num_ps_threads = 128;
|
||||
num_vs_threads = 20;
|
||||
num_gs_threads = 20;
|
||||
num_es_threads = 20;
|
||||
num_hs_threads = 20;
|
||||
num_ls_threads = 20;
|
||||
num_ps_stack_entries = 85;
|
||||
num_vs_stack_entries = 85;
|
||||
num_gs_stack_entries = 85;
|
||||
num_es_stack_entries = 85;
|
||||
num_hs_stack_entries = 85;
|
||||
num_ls_stack_entries = 85;
|
||||
break;
|
||||
case CHIP_TURKS:
|
||||
num_ps_gprs = 93;
|
||||
num_vs_gprs = 46;
|
||||
num_temp_gprs = 4;
|
||||
num_gs_gprs = 31;
|
||||
num_es_gprs = 31;
|
||||
num_hs_gprs = 23;
|
||||
num_ls_gprs = 23;
|
||||
num_ps_threads = 128;
|
||||
num_vs_threads = 20;
|
||||
num_gs_threads = 20;
|
||||
num_es_threads = 20;
|
||||
num_hs_threads = 20;
|
||||
num_ls_threads = 20;
|
||||
num_ps_stack_entries = 42;
|
||||
num_vs_stack_entries = 42;
|
||||
num_gs_stack_entries = 42;
|
||||
num_es_stack_entries = 42;
|
||||
num_hs_stack_entries = 42;
|
||||
num_ls_stack_entries = 42;
|
||||
break;
|
||||
case CHIP_CAICOS:
|
||||
num_ps_gprs = 93;
|
||||
num_vs_gprs = 46;
|
||||
num_temp_gprs = 4;
|
||||
num_gs_gprs = 31;
|
||||
num_es_gprs = 31;
|
||||
num_hs_gprs = 23;
|
||||
num_ls_gprs = 23;
|
||||
num_ps_threads = 128;
|
||||
num_vs_threads = 10;
|
||||
num_gs_threads = 10;
|
||||
num_es_threads = 10;
|
||||
num_hs_threads = 10;
|
||||
num_ls_threads = 10;
|
||||
num_ps_stack_entries = 42;
|
||||
num_vs_stack_entries = 42;
|
||||
num_gs_stack_entries = 42;
|
||||
num_es_stack_entries = 42;
|
||||
num_hs_stack_entries = 42;
|
||||
num_ls_stack_entries = 42;
|
||||
break;
|
||||
}
|
||||
|
||||
if ((rdev->family == CHIP_CEDAR) ||
|
||||
(rdev->family == CHIP_PALM) ||
|
||||
(rdev->family == CHIP_SUMO) ||
|
||||
(rdev->family == CHIP_SUMO2) ||
|
||||
(rdev->family == CHIP_CAICOS))
|
||||
sq_config = 0;
|
||||
else
|
||||
sq_config = VC_ENABLE;
|
||||
|
||||
sq_config |= (EXPORT_SRC_C |
|
||||
CS_PRIO(0) |
|
||||
LS_PRIO(0) |
|
||||
HS_PRIO(0) |
|
||||
PS_PRIO(0) |
|
||||
VS_PRIO(1) |
|
||||
GS_PRIO(2) |
|
||||
ES_PRIO(3));
|
||||
|
||||
sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
|
||||
NUM_VS_GPRS(num_vs_gprs) |
|
||||
NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
|
||||
sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
|
||||
NUM_ES_GPRS(num_es_gprs));
|
||||
sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) |
|
||||
NUM_LS_GPRS(num_ls_gprs));
|
||||
sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
|
||||
NUM_VS_THREADS(num_vs_threads) |
|
||||
NUM_GS_THREADS(num_gs_threads) |
|
||||
NUM_ES_THREADS(num_es_threads));
|
||||
sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) |
|
||||
NUM_LS_THREADS(num_ls_threads));
|
||||
sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
|
||||
NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
|
||||
sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
|
||||
NUM_ES_STACK_ENTRIES(num_es_stack_entries));
|
||||
sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
|
||||
NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
|
||||
|
||||
/* disable dyn gprs */
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
|
||||
radeon_ring_write(ring, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
|
||||
radeon_ring_write(ring, 0);
|
||||
|
||||
/* setup LDS */
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
|
||||
radeon_ring_write(ring, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2);
|
||||
radeon_ring_write(ring, 0x10001000);
|
||||
|
||||
/* SQ config */
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 11));
|
||||
radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
|
||||
radeon_ring_write(ring, sq_config);
|
||||
radeon_ring_write(ring, sq_gpr_resource_mgmt_1);
|
||||
radeon_ring_write(ring, sq_gpr_resource_mgmt_2);
|
||||
radeon_ring_write(ring, sq_gpr_resource_mgmt_3);
|
||||
radeon_ring_write(ring, 0);
|
||||
radeon_ring_write(ring, 0);
|
||||
radeon_ring_write(ring, sq_thread_resource_mgmt);
|
||||
radeon_ring_write(ring, sq_thread_resource_mgmt_2);
|
||||
radeon_ring_write(ring, sq_stack_resource_mgmt_1);
|
||||
radeon_ring_write(ring, sq_stack_resource_mgmt_2);
|
||||
radeon_ring_write(ring, sq_stack_resource_mgmt_3);
|
||||
}
|
||||
|
||||
/* CONTEXT_CONTROL */
|
||||
radeon_ring_write(ring, 0xc0012800);
|
||||
radeon_ring_write(ring, 0x80000000);
|
||||
radeon_ring_write(ring, 0x80000000);
|
||||
|
||||
/* SQ_VTX_BASE_VTX_LOC */
|
||||
radeon_ring_write(ring, 0xc0026f00);
|
||||
radeon_ring_write(ring, 0x00000000);
|
||||
radeon_ring_write(ring, 0x00000000);
|
||||
radeon_ring_write(ring, 0x00000000);
|
||||
|
||||
/* SET_SAMPLER */
|
||||
radeon_ring_write(ring, 0xc0036e00);
|
||||
radeon_ring_write(ring, 0x00000000);
|
||||
radeon_ring_write(ring, 0x00000012);
|
||||
radeon_ring_write(ring, 0x00000000);
|
||||
radeon_ring_write(ring, 0x00000000);
|
||||
|
||||
/* set to DX10/11 mode */
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
|
||||
radeon_ring_write(ring, 1);
|
||||
|
||||
/* emit an IB pointing at default state */
|
||||
dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
|
||||
gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
|
||||
radeon_ring_write(ring, gpu_addr & 0xFFFFFFFC);
|
||||
radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);
|
||||
radeon_ring_write(ring, dwords);
|
||||
|
||||
}
|
||||
|
||||
int evergreen_blit_init(struct radeon_device *rdev)
|
||||
{
|
||||
u32 obj_size;
|
||||
int i, r, dwords;
|
||||
void *ptr;
|
||||
u32 packet2s[16];
|
||||
int num_packet2s = 0;
|
||||
|
||||
rdev->r600_blit.primitives.set_render_target = set_render_target;
|
||||
rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
|
||||
rdev->r600_blit.primitives.set_shaders = set_shaders;
|
||||
rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
|
||||
rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
|
||||
rdev->r600_blit.primitives.set_scissors = set_scissors;
|
||||
rdev->r600_blit.primitives.draw_auto = draw_auto;
|
||||
rdev->r600_blit.primitives.set_default_state = set_default_state;
|
||||
|
||||
rdev->r600_blit.ring_size_common = 8; /* sync semaphore */
|
||||
rdev->r600_blit.ring_size_common += 55; /* shaders + def state */
|
||||
rdev->r600_blit.ring_size_common += 16; /* fence emit for VB IB */
|
||||
rdev->r600_blit.ring_size_common += 5; /* done copy */
|
||||
rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
|
||||
|
||||
rdev->r600_blit.ring_size_per_loop = 74;
|
||||
if (rdev->family >= CHIP_CAYMAN)
|
||||
rdev->r600_blit.ring_size_per_loop += 9; /* additional DWs for surface sync */
|
||||
|
||||
rdev->r600_blit.max_dim = 16384;
|
||||
|
||||
rdev->r600_blit.state_offset = 0;
|
||||
|
||||
if (rdev->family < CHIP_CAYMAN)
|
||||
rdev->r600_blit.state_len = evergreen_default_size;
|
||||
else
|
||||
rdev->r600_blit.state_len = cayman_default_size;
|
||||
|
||||
dwords = rdev->r600_blit.state_len;
|
||||
while (dwords & 0xf) {
|
||||
packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
|
||||
dwords++;
|
||||
}
|
||||
|
||||
obj_size = dwords * 4;
|
||||
obj_size = ALIGN(obj_size, 256);
|
||||
|
||||
rdev->r600_blit.vs_offset = obj_size;
|
||||
if (rdev->family < CHIP_CAYMAN)
|
||||
obj_size += evergreen_vs_size * 4;
|
||||
else
|
||||
obj_size += cayman_vs_size * 4;
|
||||
obj_size = ALIGN(obj_size, 256);
|
||||
|
||||
rdev->r600_blit.ps_offset = obj_size;
|
||||
if (rdev->family < CHIP_CAYMAN)
|
||||
obj_size += evergreen_ps_size * 4;
|
||||
else
|
||||
obj_size += cayman_ps_size * 4;
|
||||
obj_size = ALIGN(obj_size, 256);
|
||||
|
||||
/* pin copy shader into vram if not already initialized */
|
||||
if (!rdev->r600_blit.shader_obj) {
|
||||
r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true,
|
||||
RADEON_GEM_DOMAIN_VRAM,
|
||||
NULL, &rdev->r600_blit.shader_obj);
|
||||
if (r) {
|
||||
DRM_ERROR("evergreen failed to allocate shader\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
|
||||
if (unlikely(r != 0))
|
||||
return r;
|
||||
r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
|
||||
&rdev->r600_blit.shader_gpu_addr);
|
||||
radeon_bo_unreserve(rdev->r600_blit.shader_obj);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
|
||||
return r;
|
||||
}
|
||||
}
|
||||
|
||||
DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n",
|
||||
obj_size,
|
||||
rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
|
||||
|
||||
r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
|
||||
if (unlikely(r != 0))
|
||||
return r;
|
||||
r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
|
||||
if (r) {
|
||||
DRM_ERROR("failed to map blit object %d\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
if (rdev->family < CHIP_CAYMAN) {
|
||||
memcpy_toio(ptr + rdev->r600_blit.state_offset,
|
||||
evergreen_default_state, rdev->r600_blit.state_len * 4);
|
||||
|
||||
if (num_packet2s)
|
||||
memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
|
||||
packet2s, num_packet2s * 4);
|
||||
for (i = 0; i < evergreen_vs_size; i++)
|
||||
*(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]);
|
||||
for (i = 0; i < evergreen_ps_size; i++)
|
||||
*(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]);
|
||||
} else {
|
||||
memcpy_toio(ptr + rdev->r600_blit.state_offset,
|
||||
cayman_default_state, rdev->r600_blit.state_len * 4);
|
||||
|
||||
if (num_packet2s)
|
||||
memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
|
||||
packet2s, num_packet2s * 4);
|
||||
for (i = 0; i < cayman_vs_size; i++)
|
||||
*(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(cayman_vs[i]);
|
||||
for (i = 0; i < cayman_ps_size; i++)
|
||||
*(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(cayman_ps[i]);
|
||||
}
|
||||
radeon_bo_kunmap(rdev->r600_blit.shader_obj);
|
||||
radeon_bo_unreserve(rdev->r600_blit.shader_obj);
|
||||
|
||||
radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -300,58 +300,4 @@ const u32 evergreen_default_state[] =
|
|||
0x00000010, /* */
|
||||
};
|
||||
|
||||
const u32 evergreen_vs[] =
|
||||
{
|
||||
0x00000004,
|
||||
0x80800400,
|
||||
0x0000a03c,
|
||||
0x95000688,
|
||||
0x00004000,
|
||||
0x15200688,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x3c000000,
|
||||
0x67961001,
|
||||
#ifdef __BIG_ENDIAN
|
||||
0x000a0000,
|
||||
#else
|
||||
0x00080000,
|
||||
#endif
|
||||
0x00000000,
|
||||
0x1c000000,
|
||||
0x67961000,
|
||||
#ifdef __BIG_ENDIAN
|
||||
0x00020008,
|
||||
#else
|
||||
0x00000008,
|
||||
#endif
|
||||
0x00000000,
|
||||
};
|
||||
|
||||
const u32 evergreen_ps[] =
|
||||
{
|
||||
0x00000003,
|
||||
0xa00c0000,
|
||||
0x00000008,
|
||||
0x80400000,
|
||||
0x00000000,
|
||||
0x95200688,
|
||||
0x00380400,
|
||||
0x00146b10,
|
||||
0x00380000,
|
||||
0x20146b10,
|
||||
0x00380400,
|
||||
0x40146b00,
|
||||
0x80380000,
|
||||
0x60146b00,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000010,
|
||||
0x000d1000,
|
||||
0xb0800000,
|
||||
0x00000000,
|
||||
};
|
||||
|
||||
const u32 evergreen_ps_size = ARRAY_SIZE(evergreen_ps);
|
||||
const u32 evergreen_vs_size = ARRAY_SIZE(evergreen_vs);
|
||||
const u32 evergreen_default_size = ARRAY_SIZE(evergreen_default_state);
|
||||
|
|
|
|||
|
|
@ -2118,13 +2118,6 @@ static int cayman_startup(struct radeon_device *rdev)
|
|||
return r;
|
||||
cayman_gpu_init(rdev);
|
||||
|
||||
r = evergreen_blit_init(rdev);
|
||||
if (r) {
|
||||
r600_blit_fini(rdev);
|
||||
rdev->asic->copy.copy = NULL;
|
||||
dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
|
||||
}
|
||||
|
||||
/* allocate rlc buffers */
|
||||
if (rdev->flags & RADEON_IS_IGP) {
|
||||
rdev->rlc.reg_list = tn_rlc_save_restore_register_list;
|
||||
|
|
@ -2413,7 +2406,6 @@ int cayman_init(struct radeon_device *rdev)
|
|||
|
||||
void cayman_fini(struct radeon_device *rdev)
|
||||
{
|
||||
r600_blit_fini(rdev);
|
||||
cayman_cp_fini(rdev);
|
||||
cayman_dma_fini(rdev);
|
||||
r600_irq_fini(rdev);
|
||||
|
|
|
|||
|
|
@ -3136,25 +3136,6 @@ void r600_uvd_semaphore_emit(struct radeon_device *rdev,
|
|||
radeon_ring_write(ring, emit_wait ? 1 : 0);
|
||||
}
|
||||
|
||||
int r600_copy_blit(struct radeon_device *rdev,
|
||||
uint64_t src_offset,
|
||||
uint64_t dst_offset,
|
||||
unsigned num_gpu_pages,
|
||||
struct radeon_fence **fence)
|
||||
{
|
||||
struct radeon_semaphore *sem = NULL;
|
||||
struct radeon_sa_bo *vb = NULL;
|
||||
int r;
|
||||
|
||||
r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem);
|
||||
if (r) {
|
||||
return r;
|
||||
}
|
||||
r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb);
|
||||
r600_blit_done_copy(rdev, fence, vb, sem);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* r600_copy_cpdma - copy pages using the CP DMA engine
|
||||
*
|
||||
|
|
@ -3356,12 +3337,6 @@ static int r600_startup(struct radeon_device *rdev)
|
|||
return r;
|
||||
}
|
||||
r600_gpu_init(rdev);
|
||||
r = r600_blit_init(rdev);
|
||||
if (r) {
|
||||
r600_blit_fini(rdev);
|
||||
rdev->asic->copy.copy = NULL;
|
||||
dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
|
||||
}
|
||||
|
||||
/* allocate wb buffer */
|
||||
r = radeon_wb_init(rdev);
|
||||
|
|
@ -3574,7 +3549,6 @@ int r600_init(struct radeon_device *rdev)
|
|||
void r600_fini(struct radeon_device *rdev)
|
||||
{
|
||||
r600_audio_fini(rdev);
|
||||
r600_blit_fini(rdev);
|
||||
r600_cp_fini(rdev);
|
||||
r600_dma_fini(rdev);
|
||||
r600_irq_fini(rdev);
|
||||
|
|
|
|||
|
|
@ -31,6 +31,37 @@
|
|||
|
||||
#include "r600_blit_shaders.h"
|
||||
|
||||
/* 23 bits of float fractional data */
|
||||
#define I2F_FRAC_BITS 23
|
||||
#define I2F_MASK ((1 << I2F_FRAC_BITS) - 1)
|
||||
|
||||
/*
|
||||
* Converts unsigned integer into 32-bit IEEE floating point representation.
|
||||
* Will be exact from 0 to 2^24. Above that, we round towards zero
|
||||
* as the fractional bits will not fit in a float. (It would be better to
|
||||
* round towards even as the fpu does, but that is slower.)
|
||||
*/
|
||||
static __pure uint32_t int2float(uint32_t x)
|
||||
{
|
||||
uint32_t msb, exponent, fraction;
|
||||
|
||||
/* Zero is special */
|
||||
if (!x) return 0;
|
||||
|
||||
/* Get location of the most significant bit */
|
||||
msb = __fls(x);
|
||||
|
||||
/*
|
||||
* Use a rotate instead of a shift because that works both leftwards
|
||||
* and rightwards due to the mod(32) behaviour. This means we don't
|
||||
* need to check to see if we are above 2^24 or not.
|
||||
*/
|
||||
fraction = ror32(x, (msb - I2F_FRAC_BITS) & 0x1f) & I2F_MASK;
|
||||
exponent = (127 + msb) << I2F_FRAC_BITS;
|
||||
|
||||
return fraction + exponent;
|
||||
}
|
||||
|
||||
#define DI_PT_RECTLIST 0x11
|
||||
#define DI_INDEX_SIZE_16_BIT 0x0
|
||||
#define DI_SRC_SEL_AUTO_INDEX 0x2
|
||||
|
|
|
|||
|
|
@ -1,785 +0,0 @@
|
|||
/*
|
||||
* Copyright 2009 Advanced Micro Devices, Inc.
|
||||
* Copyright 2009 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/radeon_drm.h>
|
||||
#include "radeon.h"
|
||||
|
||||
#include "r600d.h"
|
||||
#include "r600_blit_shaders.h"
|
||||
#include "radeon_blit_common.h"
|
||||
|
||||
/* 23 bits of float fractional data */
|
||||
#define I2F_FRAC_BITS 23
|
||||
#define I2F_MASK ((1 << I2F_FRAC_BITS) - 1)
|
||||
|
||||
/*
|
||||
* Converts unsigned integer into 32-bit IEEE floating point representation.
|
||||
* Will be exact from 0 to 2^24. Above that, we round towards zero
|
||||
* as the fractional bits will not fit in a float. (It would be better to
|
||||
* round towards even as the fpu does, but that is slower.)
|
||||
*/
|
||||
__pure uint32_t int2float(uint32_t x)
|
||||
{
|
||||
uint32_t msb, exponent, fraction;
|
||||
|
||||
/* Zero is special */
|
||||
if (!x) return 0;
|
||||
|
||||
/* Get location of the most significant bit */
|
||||
msb = __fls(x);
|
||||
|
||||
/*
|
||||
* Use a rotate instead of a shift because that works both leftwards
|
||||
* and rightwards due to the mod(32) behaviour. This means we don't
|
||||
* need to check to see if we are above 2^24 or not.
|
||||
*/
|
||||
fraction = ror32(x, (msb - I2F_FRAC_BITS) & 0x1f) & I2F_MASK;
|
||||
exponent = (127 + msb) << I2F_FRAC_BITS;
|
||||
|
||||
return fraction + exponent;
|
||||
}
|
||||
|
||||
/* emits 21 on rv770+, 23 on r600 */
|
||||
static void
|
||||
set_render_target(struct radeon_device *rdev, int format,
|
||||
int w, int h, u64 gpu_addr)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
u32 cb_color_info;
|
||||
int pitch, slice;
|
||||
|
||||
h = ALIGN(h, 8);
|
||||
if (h < 8)
|
||||
h = 8;
|
||||
|
||||
cb_color_info = CB_FORMAT(format) |
|
||||
CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
|
||||
CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
|
||||
pitch = (w / 8) - 1;
|
||||
slice = ((w * h) / 64) - 1;
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
|
||||
radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, gpu_addr >> 8);
|
||||
|
||||
if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
|
||||
radeon_ring_write(ring, 2 << 0);
|
||||
}
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
|
||||
radeon_ring_write(ring, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, (pitch << 0) | (slice << 10));
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
|
||||
radeon_ring_write(ring, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, 0);
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
|
||||
radeon_ring_write(ring, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, cb_color_info);
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
|
||||
radeon_ring_write(ring, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, 0);
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
|
||||
radeon_ring_write(ring, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, 0);
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
|
||||
radeon_ring_write(ring, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, 0);
|
||||
}
|
||||
|
||||
/* emits 5dw */
|
||||
static void
|
||||
cp_set_surface_sync(struct radeon_device *rdev,
|
||||
u32 sync_type, u32 size,
|
||||
u64 mc_addr)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
u32 cp_coher_size;
|
||||
|
||||
if (size == 0xffffffff)
|
||||
cp_coher_size = 0xffffffff;
|
||||
else
|
||||
cp_coher_size = ((size + 255) >> 8);
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
|
||||
radeon_ring_write(ring, sync_type);
|
||||
radeon_ring_write(ring, cp_coher_size);
|
||||
radeon_ring_write(ring, mc_addr >> 8);
|
||||
radeon_ring_write(ring, 10); /* poll interval */
|
||||
}
|
||||
|
||||
/* emits 21dw + 1 surface sync = 26dw */
|
||||
static void
|
||||
set_shaders(struct radeon_device *rdev)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
u64 gpu_addr;
|
||||
u32 sq_pgm_resources;
|
||||
|
||||
/* setup shader regs */
|
||||
sq_pgm_resources = (1 << 0);
|
||||
|
||||
/* VS */
|
||||
gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
|
||||
radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, gpu_addr >> 8);
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
|
||||
radeon_ring_write(ring, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, sq_pgm_resources);
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
|
||||
radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, 0);
|
||||
|
||||
/* PS */
|
||||
gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
|
||||
radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, gpu_addr >> 8);
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
|
||||
radeon_ring_write(ring, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, sq_pgm_resources | (1 << 28));
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
|
||||
radeon_ring_write(ring, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, 2);
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
|
||||
radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, 0);
|
||||
|
||||
gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
|
||||
cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
|
||||
}
|
||||
|
||||
/* emits 9 + 1 sync (5) = 14*/
|
||||
static void
|
||||
set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
u32 sq_vtx_constant_word2;
|
||||
|
||||
sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
|
||||
SQ_VTXC_STRIDE(16);
|
||||
#ifdef __BIG_ENDIAN
|
||||
sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
|
||||
#endif
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
|
||||
radeon_ring_write(ring, 0x460);
|
||||
radeon_ring_write(ring, gpu_addr & 0xffffffff);
|
||||
radeon_ring_write(ring, 48 - 1);
|
||||
radeon_ring_write(ring, sq_vtx_constant_word2);
|
||||
radeon_ring_write(ring, 1 << 0);
|
||||
radeon_ring_write(ring, 0);
|
||||
radeon_ring_write(ring, 0);
|
||||
radeon_ring_write(ring, SQ_TEX_VTX_VALID_BUFFER << 30);
|
||||
|
||||
if ((rdev->family == CHIP_RV610) ||
|
||||
(rdev->family == CHIP_RV620) ||
|
||||
(rdev->family == CHIP_RS780) ||
|
||||
(rdev->family == CHIP_RS880) ||
|
||||
(rdev->family == CHIP_RV710))
|
||||
cp_set_surface_sync(rdev,
|
||||
PACKET3_TC_ACTION_ENA, 48, gpu_addr);
|
||||
else
|
||||
cp_set_surface_sync(rdev,
|
||||
PACKET3_VC_ACTION_ENA, 48, gpu_addr);
|
||||
}
|
||||
|
||||
/* emits 9 */
|
||||
static void
|
||||
set_tex_resource(struct radeon_device *rdev,
|
||||
int format, int w, int h, int pitch,
|
||||
u64 gpu_addr, u32 size)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
|
||||
|
||||
if (h < 1)
|
||||
h = 1;
|
||||
|
||||
sq_tex_resource_word0 = S_038000_DIM(V_038000_SQ_TEX_DIM_2D) |
|
||||
S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
|
||||
sq_tex_resource_word0 |= S_038000_PITCH((pitch >> 3) - 1) |
|
||||
S_038000_TEX_WIDTH(w - 1);
|
||||
|
||||
sq_tex_resource_word1 = S_038004_DATA_FORMAT(format);
|
||||
sq_tex_resource_word1 |= S_038004_TEX_HEIGHT(h - 1);
|
||||
|
||||
sq_tex_resource_word4 = S_038010_REQUEST_SIZE(1) |
|
||||
S_038010_DST_SEL_X(SQ_SEL_X) |
|
||||
S_038010_DST_SEL_Y(SQ_SEL_Y) |
|
||||
S_038010_DST_SEL_Z(SQ_SEL_Z) |
|
||||
S_038010_DST_SEL_W(SQ_SEL_W);
|
||||
|
||||
cp_set_surface_sync(rdev,
|
||||
PACKET3_TC_ACTION_ENA, size, gpu_addr);
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
|
||||
radeon_ring_write(ring, 0);
|
||||
radeon_ring_write(ring, sq_tex_resource_word0);
|
||||
radeon_ring_write(ring, sq_tex_resource_word1);
|
||||
radeon_ring_write(ring, gpu_addr >> 8);
|
||||
radeon_ring_write(ring, gpu_addr >> 8);
|
||||
radeon_ring_write(ring, sq_tex_resource_word4);
|
||||
radeon_ring_write(ring, 0);
|
||||
radeon_ring_write(ring, SQ_TEX_VTX_VALID_TEXTURE << 30);
|
||||
}
|
||||
|
||||
/* emits 12 */
|
||||
static void
|
||||
set_scissors(struct radeon_device *rdev, int x1, int y1,
|
||||
int x2, int y2)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
|
||||
radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, (x1 << 0) | (y1 << 16));
|
||||
radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
|
||||
radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
|
||||
radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
|
||||
radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
|
||||
radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
|
||||
}
|
||||
|
||||
/* emits 10 */
|
||||
static void
|
||||
draw_auto(struct radeon_device *rdev)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
|
||||
radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, DI_PT_RECTLIST);
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));
|
||||
radeon_ring_write(ring,
|
||||
#ifdef __BIG_ENDIAN
|
||||
(2 << 2) |
|
||||
#endif
|
||||
DI_INDEX_SIZE_16_BIT);
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));
|
||||
radeon_ring_write(ring, 1);
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
|
||||
radeon_ring_write(ring, 3);
|
||||
radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);
|
||||
|
||||
}
|
||||
|
||||
/* emits 14 */
|
||||
static void
|
||||
set_default_state(struct radeon_device *rdev)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
|
||||
u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
|
||||
int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
|
||||
int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
|
||||
int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
|
||||
u64 gpu_addr;
|
||||
int dwords;
|
||||
|
||||
switch (rdev->family) {
|
||||
case CHIP_R600:
|
||||
num_ps_gprs = 192;
|
||||
num_vs_gprs = 56;
|
||||
num_temp_gprs = 4;
|
||||
num_gs_gprs = 0;
|
||||
num_es_gprs = 0;
|
||||
num_ps_threads = 136;
|
||||
num_vs_threads = 48;
|
||||
num_gs_threads = 4;
|
||||
num_es_threads = 4;
|
||||
num_ps_stack_entries = 128;
|
||||
num_vs_stack_entries = 128;
|
||||
num_gs_stack_entries = 0;
|
||||
num_es_stack_entries = 0;
|
||||
break;
|
||||
case CHIP_RV630:
|
||||
case CHIP_RV635:
|
||||
num_ps_gprs = 84;
|
||||
num_vs_gprs = 36;
|
||||
num_temp_gprs = 4;
|
||||
num_gs_gprs = 0;
|
||||
num_es_gprs = 0;
|
||||
num_ps_threads = 144;
|
||||
num_vs_threads = 40;
|
||||
num_gs_threads = 4;
|
||||
num_es_threads = 4;
|
||||
num_ps_stack_entries = 40;
|
||||
num_vs_stack_entries = 40;
|
||||
num_gs_stack_entries = 32;
|
||||
num_es_stack_entries = 16;
|
||||
break;
|
||||
case CHIP_RV610:
|
||||
case CHIP_RV620:
|
||||
case CHIP_RS780:
|
||||
case CHIP_RS880:
|
||||
default:
|
||||
num_ps_gprs = 84;
|
||||
num_vs_gprs = 36;
|
||||
num_temp_gprs = 4;
|
||||
num_gs_gprs = 0;
|
||||
num_es_gprs = 0;
|
||||
num_ps_threads = 136;
|
||||
num_vs_threads = 48;
|
||||
num_gs_threads = 4;
|
||||
num_es_threads = 4;
|
||||
num_ps_stack_entries = 40;
|
||||
num_vs_stack_entries = 40;
|
||||
num_gs_stack_entries = 32;
|
||||
num_es_stack_entries = 16;
|
||||
break;
|
||||
case CHIP_RV670:
|
||||
num_ps_gprs = 144;
|
||||
num_vs_gprs = 40;
|
||||
num_temp_gprs = 4;
|
||||
num_gs_gprs = 0;
|
||||
num_es_gprs = 0;
|
||||
num_ps_threads = 136;
|
||||
num_vs_threads = 48;
|
||||
num_gs_threads = 4;
|
||||
num_es_threads = 4;
|
||||
num_ps_stack_entries = 40;
|
||||
num_vs_stack_entries = 40;
|
||||
num_gs_stack_entries = 32;
|
||||
num_es_stack_entries = 16;
|
||||
break;
|
||||
case CHIP_RV770:
|
||||
num_ps_gprs = 192;
|
||||
num_vs_gprs = 56;
|
||||
num_temp_gprs = 4;
|
||||
num_gs_gprs = 0;
|
||||
num_es_gprs = 0;
|
||||
num_ps_threads = 188;
|
||||
num_vs_threads = 60;
|
||||
num_gs_threads = 0;
|
||||
num_es_threads = 0;
|
||||
num_ps_stack_entries = 256;
|
||||
num_vs_stack_entries = 256;
|
||||
num_gs_stack_entries = 0;
|
||||
num_es_stack_entries = 0;
|
||||
break;
|
||||
case CHIP_RV730:
|
||||
case CHIP_RV740:
|
||||
num_ps_gprs = 84;
|
||||
num_vs_gprs = 36;
|
||||
num_temp_gprs = 4;
|
||||
num_gs_gprs = 0;
|
||||
num_es_gprs = 0;
|
||||
num_ps_threads = 188;
|
||||
num_vs_threads = 60;
|
||||
num_gs_threads = 0;
|
||||
num_es_threads = 0;
|
||||
num_ps_stack_entries = 128;
|
||||
num_vs_stack_entries = 128;
|
||||
num_gs_stack_entries = 0;
|
||||
num_es_stack_entries = 0;
|
||||
break;
|
||||
case CHIP_RV710:
|
||||
num_ps_gprs = 192;
|
||||
num_vs_gprs = 56;
|
||||
num_temp_gprs = 4;
|
||||
num_gs_gprs = 0;
|
||||
num_es_gprs = 0;
|
||||
num_ps_threads = 144;
|
||||
num_vs_threads = 48;
|
||||
num_gs_threads = 0;
|
||||
num_es_threads = 0;
|
||||
num_ps_stack_entries = 128;
|
||||
num_vs_stack_entries = 128;
|
||||
num_gs_stack_entries = 0;
|
||||
num_es_stack_entries = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
if ((rdev->family == CHIP_RV610) ||
|
||||
(rdev->family == CHIP_RV620) ||
|
||||
(rdev->family == CHIP_RS780) ||
|
||||
(rdev->family == CHIP_RS880) ||
|
||||
(rdev->family == CHIP_RV710))
|
||||
sq_config = 0;
|
||||
else
|
||||
sq_config = VC_ENABLE;
|
||||
|
||||
sq_config |= (DX9_CONSTS |
|
||||
ALU_INST_PREFER_VECTOR |
|
||||
PS_PRIO(0) |
|
||||
VS_PRIO(1) |
|
||||
GS_PRIO(2) |
|
||||
ES_PRIO(3));
|
||||
|
||||
sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
|
||||
NUM_VS_GPRS(num_vs_gprs) |
|
||||
NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
|
||||
sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
|
||||
NUM_ES_GPRS(num_es_gprs));
|
||||
sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
|
||||
NUM_VS_THREADS(num_vs_threads) |
|
||||
NUM_GS_THREADS(num_gs_threads) |
|
||||
NUM_ES_THREADS(num_es_threads));
|
||||
sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
|
||||
NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
|
||||
sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
|
||||
NUM_ES_STACK_ENTRIES(num_es_stack_entries));
|
||||
|
||||
/* emit an IB pointing at default state */
|
||||
dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
|
||||
gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
|
||||
radeon_ring_write(ring,
|
||||
#ifdef __BIG_ENDIAN
|
||||
(2 << 0) |
|
||||
#endif
|
||||
(gpu_addr & 0xFFFFFFFC));
|
||||
radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);
|
||||
radeon_ring_write(ring, dwords);
|
||||
|
||||
/* SQ config */
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 6));
|
||||
radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
|
||||
radeon_ring_write(ring, sq_config);
|
||||
radeon_ring_write(ring, sq_gpr_resource_mgmt_1);
|
||||
radeon_ring_write(ring, sq_gpr_resource_mgmt_2);
|
||||
radeon_ring_write(ring, sq_thread_resource_mgmt);
|
||||
radeon_ring_write(ring, sq_stack_resource_mgmt_1);
|
||||
radeon_ring_write(ring, sq_stack_resource_mgmt_2);
|
||||
}
|
||||
|
||||
int r600_blit_init(struct radeon_device *rdev)
|
||||
{
|
||||
u32 obj_size;
|
||||
int i, r, dwords;
|
||||
void *ptr;
|
||||
u32 packet2s[16];
|
||||
int num_packet2s = 0;
|
||||
|
||||
rdev->r600_blit.primitives.set_render_target = set_render_target;
|
||||
rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
|
||||
rdev->r600_blit.primitives.set_shaders = set_shaders;
|
||||
rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
|
||||
rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
|
||||
rdev->r600_blit.primitives.set_scissors = set_scissors;
|
||||
rdev->r600_blit.primitives.draw_auto = draw_auto;
|
||||
rdev->r600_blit.primitives.set_default_state = set_default_state;
|
||||
|
||||
rdev->r600_blit.ring_size_common = 8; /* sync semaphore */
|
||||
rdev->r600_blit.ring_size_common += 40; /* shaders + def state */
|
||||
rdev->r600_blit.ring_size_common += 5; /* done copy */
|
||||
rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
|
||||
|
||||
rdev->r600_blit.ring_size_per_loop = 76;
|
||||
/* set_render_target emits 2 extra dwords on rv6xx */
|
||||
if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
|
||||
rdev->r600_blit.ring_size_per_loop += 2;
|
||||
|
||||
rdev->r600_blit.max_dim = 8192;
|
||||
|
||||
rdev->r600_blit.state_offset = 0;
|
||||
|
||||
if (rdev->family >= CHIP_RV770)
|
||||
rdev->r600_blit.state_len = r7xx_default_size;
|
||||
else
|
||||
rdev->r600_blit.state_len = r6xx_default_size;
|
||||
|
||||
dwords = rdev->r600_blit.state_len;
|
||||
while (dwords & 0xf) {
|
||||
packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
|
||||
dwords++;
|
||||
}
|
||||
|
||||
obj_size = dwords * 4;
|
||||
obj_size = ALIGN(obj_size, 256);
|
||||
|
||||
rdev->r600_blit.vs_offset = obj_size;
|
||||
obj_size += r6xx_vs_size * 4;
|
||||
obj_size = ALIGN(obj_size, 256);
|
||||
|
||||
rdev->r600_blit.ps_offset = obj_size;
|
||||
obj_size += r6xx_ps_size * 4;
|
||||
obj_size = ALIGN(obj_size, 256);
|
||||
|
||||
/* pin copy shader into vram if not already initialized */
|
||||
if (rdev->r600_blit.shader_obj == NULL) {
|
||||
r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true,
|
||||
RADEON_GEM_DOMAIN_VRAM,
|
||||
NULL, &rdev->r600_blit.shader_obj);
|
||||
if (r) {
|
||||
DRM_ERROR("r600 failed to allocate shader\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
|
||||
if (unlikely(r != 0))
|
||||
return r;
|
||||
r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
|
||||
&rdev->r600_blit.shader_gpu_addr);
|
||||
radeon_bo_unreserve(rdev->r600_blit.shader_obj);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
|
||||
return r;
|
||||
}
|
||||
}
|
||||
|
||||
DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
|
||||
obj_size,
|
||||
rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
|
||||
|
||||
r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
|
||||
if (unlikely(r != 0))
|
||||
return r;
|
||||
r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
|
||||
if (r) {
|
||||
DRM_ERROR("failed to map blit object %d\n", r);
|
||||
return r;
|
||||
}
|
||||
if (rdev->family >= CHIP_RV770)
|
||||
memcpy_toio(ptr + rdev->r600_blit.state_offset,
|
||||
r7xx_default_state, rdev->r600_blit.state_len * 4);
|
||||
else
|
||||
memcpy_toio(ptr + rdev->r600_blit.state_offset,
|
||||
r6xx_default_state, rdev->r600_blit.state_len * 4);
|
||||
if (num_packet2s)
|
||||
memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
|
||||
packet2s, num_packet2s * 4);
|
||||
for (i = 0; i < r6xx_vs_size; i++)
|
||||
*(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]);
|
||||
for (i = 0; i < r6xx_ps_size; i++)
|
||||
*(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]);
|
||||
radeon_bo_kunmap(rdev->r600_blit.shader_obj);
|
||||
radeon_bo_unreserve(rdev->r600_blit.shader_obj);
|
||||
|
||||
radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void r600_blit_fini(struct radeon_device *rdev)
|
||||
{
|
||||
int r;
|
||||
|
||||
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
|
||||
if (rdev->r600_blit.shader_obj == NULL)
|
||||
return;
|
||||
/* If we can't reserve the bo, unref should be enough to destroy
|
||||
* it when it becomes idle.
|
||||
*/
|
||||
r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
|
||||
if (!r) {
|
||||
radeon_bo_unpin(rdev->r600_blit.shader_obj);
|
||||
radeon_bo_unreserve(rdev->r600_blit.shader_obj);
|
||||
}
|
||||
radeon_bo_unref(&rdev->r600_blit.shader_obj);
|
||||
}
|
||||
|
||||
static unsigned r600_blit_create_rect(unsigned num_gpu_pages,
|
||||
int *width, int *height, int max_dim)
|
||||
{
|
||||
unsigned max_pages;
|
||||
unsigned pages = num_gpu_pages;
|
||||
int w, h;
|
||||
|
||||
if (num_gpu_pages == 0) {
|
||||
/* not supposed to be called with no pages, but just in case */
|
||||
h = 0;
|
||||
w = 0;
|
||||
pages = 0;
|
||||
WARN_ON(1);
|
||||
} else {
|
||||
int rect_order = 2;
|
||||
h = RECT_UNIT_H;
|
||||
while (num_gpu_pages / rect_order) {
|
||||
h *= 2;
|
||||
rect_order *= 4;
|
||||
if (h >= max_dim) {
|
||||
h = max_dim;
|
||||
break;
|
||||
}
|
||||
}
|
||||
max_pages = (max_dim * h) / (RECT_UNIT_W * RECT_UNIT_H);
|
||||
if (pages > max_pages)
|
||||
pages = max_pages;
|
||||
w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h;
|
||||
w = (w / RECT_UNIT_W) * RECT_UNIT_W;
|
||||
pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H);
|
||||
BUG_ON(pages == 0);
|
||||
}
|
||||
|
||||
|
||||
DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h, w, pages);
|
||||
|
||||
/* return width and height only of the caller wants it */
|
||||
if (height)
|
||||
*height = h;
|
||||
if (width)
|
||||
*width = w;
|
||||
|
||||
return pages;
|
||||
}
|
||||
|
||||
|
||||
int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
|
||||
struct radeon_fence **fence, struct radeon_sa_bo **vb,
|
||||
struct radeon_semaphore **sem)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
int r;
|
||||
int ring_size;
|
||||
int num_loops = 0;
|
||||
int dwords_per_loop = rdev->r600_blit.ring_size_per_loop;
|
||||
|
||||
/* num loops */
|
||||
while (num_gpu_pages) {
|
||||
num_gpu_pages -=
|
||||
r600_blit_create_rect(num_gpu_pages, NULL, NULL,
|
||||
rdev->r600_blit.max_dim);
|
||||
num_loops++;
|
||||
}
|
||||
|
||||
/* 48 bytes for vertex per loop */
|
||||
r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, vb,
|
||||
(num_loops*48)+256, 256, true);
|
||||
if (r) {
|
||||
return r;
|
||||
}
|
||||
|
||||
r = radeon_semaphore_create(rdev, sem);
|
||||
if (r) {
|
||||
radeon_sa_bo_free(rdev, vb, NULL);
|
||||
return r;
|
||||
}
|
||||
|
||||
/* calculate number of loops correctly */
|
||||
ring_size = num_loops * dwords_per_loop;
|
||||
ring_size += rdev->r600_blit.ring_size_common;
|
||||
r = radeon_ring_lock(rdev, ring, ring_size);
|
||||
if (r) {
|
||||
radeon_sa_bo_free(rdev, vb, NULL);
|
||||
radeon_semaphore_free(rdev, sem, NULL);
|
||||
return r;
|
||||
}
|
||||
|
||||
if (radeon_fence_need_sync(*fence, RADEON_RING_TYPE_GFX_INDEX)) {
|
||||
radeon_semaphore_sync_rings(rdev, *sem, (*fence)->ring,
|
||||
RADEON_RING_TYPE_GFX_INDEX);
|
||||
radeon_fence_note_sync(*fence, RADEON_RING_TYPE_GFX_INDEX);
|
||||
} else {
|
||||
radeon_semaphore_free(rdev, sem, NULL);
|
||||
}
|
||||
|
||||
rdev->r600_blit.primitives.set_default_state(rdev);
|
||||
rdev->r600_blit.primitives.set_shaders(rdev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence,
|
||||
struct radeon_sa_bo *vb, struct radeon_semaphore *sem)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
int r;
|
||||
|
||||
r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
|
||||
if (r) {
|
||||
radeon_ring_unlock_undo(rdev, ring);
|
||||
return;
|
||||
}
|
||||
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_sa_bo_free(rdev, &vb, *fence);
|
||||
radeon_semaphore_free(rdev, &sem, *fence);
|
||||
}
|
||||
|
||||
void r600_kms_blit_copy(struct radeon_device *rdev,
|
||||
u64 src_gpu_addr, u64 dst_gpu_addr,
|
||||
unsigned num_gpu_pages,
|
||||
struct radeon_sa_bo *vb)
|
||||
{
|
||||
u64 vb_gpu_addr;
|
||||
u32 *vb_cpu_addr;
|
||||
|
||||
DRM_DEBUG("emitting copy %16llx %16llx %d\n",
|
||||
src_gpu_addr, dst_gpu_addr, num_gpu_pages);
|
||||
vb_cpu_addr = (u32 *)radeon_sa_bo_cpu_addr(vb);
|
||||
vb_gpu_addr = radeon_sa_bo_gpu_addr(vb);
|
||||
|
||||
while (num_gpu_pages) {
|
||||
int w, h;
|
||||
unsigned size_in_bytes;
|
||||
unsigned pages_per_loop =
|
||||
r600_blit_create_rect(num_gpu_pages, &w, &h,
|
||||
rdev->r600_blit.max_dim);
|
||||
|
||||
size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE;
|
||||
DRM_DEBUG("rectangle w=%d h=%d\n", w, h);
|
||||
|
||||
vb_cpu_addr[0] = 0;
|
||||
vb_cpu_addr[1] = 0;
|
||||
vb_cpu_addr[2] = 0;
|
||||
vb_cpu_addr[3] = 0;
|
||||
|
||||
vb_cpu_addr[4] = 0;
|
||||
vb_cpu_addr[5] = int2float(h);
|
||||
vb_cpu_addr[6] = 0;
|
||||
vb_cpu_addr[7] = int2float(h);
|
||||
|
||||
vb_cpu_addr[8] = int2float(w);
|
||||
vb_cpu_addr[9] = int2float(h);
|
||||
vb_cpu_addr[10] = int2float(w);
|
||||
vb_cpu_addr[11] = int2float(h);
|
||||
|
||||
rdev->r600_blit.primitives.set_tex_resource(rdev, FMT_8_8_8_8,
|
||||
w, h, w, src_gpu_addr, size_in_bytes);
|
||||
rdev->r600_blit.primitives.set_render_target(rdev, COLOR_8_8_8_8,
|
||||
w, h, dst_gpu_addr);
|
||||
rdev->r600_blit.primitives.set_scissors(rdev, 0, 0, w, h);
|
||||
rdev->r600_blit.primitives.set_vtx_resource(rdev, vb_gpu_addr);
|
||||
rdev->r600_blit.primitives.draw_auto(rdev);
|
||||
rdev->r600_blit.primitives.cp_set_surface_sync(rdev,
|
||||
PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
|
||||
size_in_bytes, dst_gpu_addr);
|
||||
|
||||
vb_cpu_addr += 12;
|
||||
vb_gpu_addr += 4*12;
|
||||
src_gpu_addr += size_in_bytes;
|
||||
dst_gpu_addr += size_in_bytes;
|
||||
num_gpu_pages -= pages_per_loop;
|
||||
}
|
||||
}
|
||||
|
|
@ -35,5 +35,4 @@ extern const u32 r6xx_default_state[];
|
|||
extern const u32 r6xx_ps_size, r6xx_vs_size;
|
||||
extern const u32 r6xx_default_size, r7xx_default_size;
|
||||
|
||||
__pure uint32_t int2float(uint32_t x);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -844,35 +844,6 @@ struct r600_ih {
|
|||
bool enabled;
|
||||
};
|
||||
|
||||
struct r600_blit_cp_primitives {
|
||||
void (*set_render_target)(struct radeon_device *rdev, int format,
|
||||
int w, int h, u64 gpu_addr);
|
||||
void (*cp_set_surface_sync)(struct radeon_device *rdev,
|
||||
u32 sync_type, u32 size,
|
||||
u64 mc_addr);
|
||||
void (*set_shaders)(struct radeon_device *rdev);
|
||||
void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
|
||||
void (*set_tex_resource)(struct radeon_device *rdev,
|
||||
int format, int w, int h, int pitch,
|
||||
u64 gpu_addr, u32 size);
|
||||
void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
|
||||
int x2, int y2);
|
||||
void (*draw_auto)(struct radeon_device *rdev);
|
||||
void (*set_default_state)(struct radeon_device *rdev);
|
||||
};
|
||||
|
||||
struct r600_blit {
|
||||
struct radeon_bo *shader_obj;
|
||||
struct r600_blit_cp_primitives primitives;
|
||||
int max_dim;
|
||||
int ring_size_common;
|
||||
int ring_size_per_loop;
|
||||
u64 shader_gpu_addr;
|
||||
u32 vs_offset, ps_offset;
|
||||
u32 state_offset;
|
||||
u32 state_len;
|
||||
};
|
||||
|
||||
/*
|
||||
* RLC stuff
|
||||
*/
|
||||
|
|
@ -2066,7 +2037,6 @@ struct radeon_device {
|
|||
const struct firmware *sdma_fw; /* CIK SDMA firmware */
|
||||
const struct firmware *smc_fw; /* SMC firmware */
|
||||
const struct firmware *uvd_fw; /* UVD firmware */
|
||||
struct r600_blit r600_blit;
|
||||
struct r600_vram_scratch vram_scratch;
|
||||
int msi_enabled; /* msi enabled */
|
||||
struct r600_ih ih; /* r6/700 interrupt ring */
|
||||
|
|
|
|||
|
|
@ -337,9 +337,6 @@ void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
|
|||
int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
|
||||
int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
|
||||
int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
|
||||
int r600_copy_blit(struct radeon_device *rdev,
|
||||
uint64_t src_offset, uint64_t dst_offset,
|
||||
unsigned num_gpu_pages, struct radeon_fence **fence);
|
||||
int r600_copy_cpdma(struct radeon_device *rdev,
|
||||
uint64_t src_offset, uint64_t dst_offset,
|
||||
unsigned num_gpu_pages, struct radeon_fence **fence);
|
||||
|
|
@ -371,8 +368,6 @@ int r600_count_pipe_bits(uint32_t val);
|
|||
int r600_mc_wait_for_idle(struct radeon_device *rdev);
|
||||
int r600_pcie_gart_init(struct radeon_device *rdev);
|
||||
void r600_scratch_init(struct radeon_device *rdev);
|
||||
int r600_blit_init(struct radeon_device *rdev);
|
||||
void r600_blit_fini(struct radeon_device *rdev);
|
||||
int r600_init_microcode(struct radeon_device *rdev);
|
||||
/* r600 irq */
|
||||
int r600_irq_process(struct radeon_device *rdev);
|
||||
|
|
@ -391,16 +386,6 @@ int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
|
|||
void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
|
||||
void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
|
||||
void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
|
||||
/* r600 blit */
|
||||
int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
|
||||
struct radeon_fence **fence, struct radeon_sa_bo **vb,
|
||||
struct radeon_semaphore **sem);
|
||||
void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence,
|
||||
struct radeon_sa_bo *vb, struct radeon_semaphore *sem);
|
||||
void r600_kms_blit_copy(struct radeon_device *rdev,
|
||||
u64 src_gpu_addr, u64 dst_gpu_addr,
|
||||
unsigned num_gpu_pages,
|
||||
struct radeon_sa_bo *vb);
|
||||
int r600_mc_wait_for_idle(struct radeon_device *rdev);
|
||||
u32 r600_get_xclk(struct radeon_device *rdev);
|
||||
uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
|
||||
|
|
@ -530,7 +515,6 @@ extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_ba
|
|||
extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
|
||||
extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
|
||||
void evergreen_disable_interrupt_state(struct radeon_device *rdev);
|
||||
int evergreen_blit_init(struct radeon_device *rdev);
|
||||
int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
|
||||
void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
|
||||
struct radeon_fence *fence);
|
||||
|
|
|
|||
|
|
@ -1,44 +0,0 @@
|
|||
/*
|
||||
* Copyright 2009 Advanced Micro Devices, Inc.
|
||||
* Copyright 2009 Red Hat Inc.
|
||||
* Copyright 2012 Alcatel-Lucent, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __RADEON_BLIT_COMMON_H__
|
||||
|
||||
#define DI_PT_RECTLIST 0x11
|
||||
#define DI_INDEX_SIZE_16_BIT 0x0
|
||||
#define DI_SRC_SEL_AUTO_INDEX 0x2
|
||||
|
||||
#define FMT_8 0x1
|
||||
#define FMT_5_6_5 0x8
|
||||
#define FMT_8_8_8_8 0x1a
|
||||
#define COLOR_8 0x1
|
||||
#define COLOR_5_6_5 0x8
|
||||
#define COLOR_8_8_8_8 0x1a
|
||||
|
||||
#define RECT_UNIT_H 32
|
||||
#define RECT_UNIT_W (RADEON_GPU_PAGE_SIZE / 4 / RECT_UNIT_H)
|
||||
|
||||
#define __RADEON_BLIT_COMMON_H__
|
||||
#endif
|
||||
|
|
@ -1852,12 +1852,6 @@ static int rv770_startup(struct radeon_device *rdev)
|
|||
}
|
||||
|
||||
rv770_gpu_init(rdev);
|
||||
r = r600_blit_init(rdev);
|
||||
if (r) {
|
||||
r600_blit_fini(rdev);
|
||||
rdev->asic->copy.copy = NULL;
|
||||
dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
|
||||
}
|
||||
|
||||
/* allocate wb buffer */
|
||||
r = radeon_wb_init(rdev);
|
||||
|
|
@ -2092,7 +2086,6 @@ int rv770_init(struct radeon_device *rdev)
|
|||
|
||||
void rv770_fini(struct radeon_device *rdev)
|
||||
{
|
||||
r600_blit_fini(rdev);
|
||||
r700_cp_fini(rdev);
|
||||
r600_dma_fini(rdev);
|
||||
r600_irq_fini(rdev);
|
||||
|
|
|
|||
Loading…
Reference in a new issue