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ARM: dove: add clock gating control
This patch adds clock gates from the clock gating control register available on dove. All clock gates are hooked up to tclk, except for gigabit ethernet controller (ge) which is a child of gephy to allow both enabled/disabled at the same time. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Sebastian Hesselbarth
Jason Cooper
parent
5817d10b8b
commit
521674718a
2 changed files with 92 additions and 19 deletions
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@ -24,6 +24,7 @@
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#include <asm/mach/time.h>
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#include <asm/mach/pci.h>
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#include <mach/dove.h>
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#include <mach/pm.h>
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#include <mach/bridge-regs.h>
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#include <asm/mach/arch.h>
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#include <linux/irq.h>
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@ -69,14 +70,68 @@ void __init dove_map_io(void)
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* CLK tree
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****************************************************************************/
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static int dove_tclk;
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static DEFINE_SPINLOCK(gating_lock);
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static struct clk *tclk;
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static struct clk __init *dove_register_gate(const char *name,
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const char *parent, u8 bit_idx)
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{
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return clk_register_gate(NULL, name, parent, 0,
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(void __iomem *)CLOCK_GATING_CONTROL,
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bit_idx, 0, &gating_lock);
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}
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static void __init dove_clk_init(void)
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{
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struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
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struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
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struct clk *xor0, *xor1, *ge, *gephy;
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tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
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dove_tclk);
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orion_clkdev_init(tclk);
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usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
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usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
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sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
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pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
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pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
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sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
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sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
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nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
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camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
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i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
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i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
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crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
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ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
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pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
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xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
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xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
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gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
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ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
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orion_clkdev_add(NULL, "orion_spi.0", tclk);
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orion_clkdev_add(NULL, "orion_spi.1", tclk);
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orion_clkdev_add(NULL, "orion_wdt", tclk);
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orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
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orion_clkdev_add(NULL, "orion-ehci.0", usb0);
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orion_clkdev_add(NULL, "orion-ehci.1", usb1);
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orion_clkdev_add(NULL, "mv643xx_eth.0", ge);
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orion_clkdev_add("0", "sata_mv.0", sata);
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orion_clkdev_add("0", "pcie", pex0);
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orion_clkdev_add("1", "pcie", pex1);
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orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
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orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
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orion_clkdev_add(NULL, "orion_nand", nand);
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orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
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orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
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orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
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orion_clkdev_add(NULL, "mv_crypto", crypto);
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orion_clkdev_add(NULL, "dove-ac97", ac97);
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orion_clkdev_add(NULL, "dove-pdma", pdma);
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orion_clkdev_add(NULL, "mv_xor_shared.0", xor0);
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orion_clkdev_add(NULL, "mv_xor_shared.1", xor1);
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}
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/*****************************************************************************
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@ -13,24 +13,42 @@
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#include <mach/irqs.h>
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#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)
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#define CLOCK_GATING_USB0_MASK (1 << 0)
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#define CLOCK_GATING_USB1_MASK (1 << 1)
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#define CLOCK_GATING_GBE_MASK (1 << 2)
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#define CLOCK_GATING_SATA_MASK (1 << 3)
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#define CLOCK_GATING_PCIE0_MASK (1 << 4)
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#define CLOCK_GATING_PCIE1_MASK (1 << 5)
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#define CLOCK_GATING_SDIO0_MASK (1 << 8)
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#define CLOCK_GATING_SDIO1_MASK (1 << 9)
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#define CLOCK_GATING_NAND_MASK (1 << 10)
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#define CLOCK_GATING_CAMERA_MASK (1 << 11)
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#define CLOCK_GATING_I2S0_MASK (1 << 12)
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#define CLOCK_GATING_I2S1_MASK (1 << 13)
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#define CLOCK_GATING_CRYPTO_MASK (1 << 15)
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#define CLOCK_GATING_AC97_MASK (1 << 21)
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#define CLOCK_GATING_PDMA_MASK (1 << 22)
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#define CLOCK_GATING_XOR0_MASK (1 << 23)
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#define CLOCK_GATING_XOR1_MASK (1 << 24)
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#define CLOCK_GATING_GIGA_PHY_MASK (1 << 30)
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#define CLOCK_GATING_BIT_USB0 0
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#define CLOCK_GATING_BIT_USB1 1
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#define CLOCK_GATING_BIT_GBE 2
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#define CLOCK_GATING_BIT_SATA 3
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#define CLOCK_GATING_BIT_PCIE0 4
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#define CLOCK_GATING_BIT_PCIE1 5
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#define CLOCK_GATING_BIT_SDIO0 8
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#define CLOCK_GATING_BIT_SDIO1 9
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#define CLOCK_GATING_BIT_NAND 10
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#define CLOCK_GATING_BIT_CAMERA 11
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#define CLOCK_GATING_BIT_I2S0 12
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#define CLOCK_GATING_BIT_I2S1 13
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#define CLOCK_GATING_BIT_CRYPTO 15
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#define CLOCK_GATING_BIT_AC97 21
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#define CLOCK_GATING_BIT_PDMA 22
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#define CLOCK_GATING_BIT_XOR0 23
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#define CLOCK_GATING_BIT_XOR1 24
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#define CLOCK_GATING_BIT_GIGA_PHY 30
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#define CLOCK_GATING_USB0_MASK (1 << CLOCK_GATING_BIT_USB0)
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#define CLOCK_GATING_USB1_MASK (1 << CLOCK_GATING_BIT_USB1)
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#define CLOCK_GATING_GBE_MASK (1 << CLOCK_GATING_BIT_GBE)
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#define CLOCK_GATING_SATA_MASK (1 << CLOCK_GATING_BIT_SATA)
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#define CLOCK_GATING_PCIE0_MASK (1 << CLOCK_GATING_BIT_PCIE0)
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#define CLOCK_GATING_PCIE1_MASK (1 << CLOCK_GATING_BIT_PCIE1)
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#define CLOCK_GATING_SDIO0_MASK (1 << CLOCK_GATING_BIT_SDIO0)
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#define CLOCK_GATING_SDIO1_MASK (1 << CLOCK_GATING_BIT_SDIO1)
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#define CLOCK_GATING_NAND_MASK (1 << CLOCK_GATING_BIT_NAND)
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#define CLOCK_GATING_CAMERA_MASK (1 << CLOCK_GATING_BIT_CAMERA)
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#define CLOCK_GATING_I2S0_MASK (1 << CLOCK_GATING_BIT_I2S0)
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#define CLOCK_GATING_I2S1_MASK (1 << CLOCK_GATING_BIT_I2S1)
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#define CLOCK_GATING_CRYPTO_MASK (1 << CLOCK_GATING_BIT_CRYPTO)
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#define CLOCK_GATING_AC97_MASK (1 << CLOCK_GATING_BIT_AC97)
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#define CLOCK_GATING_PDMA_MASK (1 << CLOCK_GATING_BIT_PDMA)
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#define CLOCK_GATING_XOR0_MASK (1 << CLOCK_GATING_BIT_XOR0)
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#define CLOCK_GATING_XOR1_MASK (1 << CLOCK_GATING_BIT_XOR1)
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#define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY)
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#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)
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#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54)
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