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net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX
The SJA1110 contains two types of integrated PHYs: one 100base-TX PHY and multiple 100base-T1 PHYs. The access procedure for the 100base-T1 PHYs is also different than it is for the 100base-TX one. So we register 2 MDIO buses, one for the base-TX and the other for the base-T1. Each bus has an OF node which is a child of the "mdio" subnode of the switch, and they are recognized by compatible string. Cc: Russell King <linux@armlinux.org.uk> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vladimir Oltean
David S. Miller
parent
ceec8bc098
commit
5a8f09748e
5 changed files with 358 additions and 1 deletions
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@ -4,6 +4,7 @@ obj-$(CONFIG_NET_DSA_SJA1105) += sja1105.o
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sja1105-objs := \
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sja1105_spi.o \
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sja1105_main.o \
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sja1105_mdio.o \
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sja1105_flower.o \
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sja1105_ethtool.o \
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sja1105_devlink.o \
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@ -67,6 +67,12 @@ struct sja1105_regs {
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u64 rmii_ref_clk[SJA1105_MAX_NUM_PORTS];
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u64 rmii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
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u64 stats[__MAX_SJA1105_STATS_AREA][SJA1105_MAX_NUM_PORTS];
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u64 mdio_100base_tx;
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u64 mdio_100base_t1;
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};
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struct sja1105_mdio_private {
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struct sja1105_private *priv;
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};
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enum {
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@ -78,6 +84,12 @@ enum {
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SJA1105_SPEED_MAX,
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};
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enum sja1105_internal_phy_t {
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SJA1105_NO_PHY = 0,
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SJA1105_PHY_BASE_TX,
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SJA1105_PHY_BASE_T1,
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};
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struct sja1105_info {
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u64 device_id;
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/* Needed for distinction between P and R, and between Q and S
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@ -123,6 +135,7 @@ struct sja1105_info {
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bool supports_rgmii[SJA1105_MAX_NUM_PORTS];
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bool supports_sgmii[SJA1105_MAX_NUM_PORTS];
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bool supports_2500basex[SJA1105_MAX_NUM_PORTS];
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enum sja1105_internal_phy_t internal_phy[SJA1105_MAX_NUM_PORTS];
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const u64 port_speed[SJA1105_SPEED_MAX];
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};
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@ -246,6 +259,8 @@ struct sja1105_private {
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enum sja1105_vlan_state vlan_state;
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struct devlink_region **regions;
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struct sja1105_cbs_entry *cbs;
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struct mii_bus *mdio_base_t1;
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struct mii_bus *mdio_base_tx;
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struct sja1105_tagger_data tagger_data;
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struct sja1105_ptp_data ptp_data;
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struct sja1105_tas_data tas_data;
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@ -275,6 +290,10 @@ int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
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struct netlink_ext_ack *extack);
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void sja1105_frame_memory_partitioning(struct sja1105_private *priv);
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/* From sja1105_mdio.c */
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int sja1105_mdiobus_register(struct dsa_switch *ds);
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void sja1105_mdiobus_unregister(struct dsa_switch *ds);
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/* From sja1105_devlink.c */
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int sja1105_devlink_setup(struct dsa_switch *ds);
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void sja1105_devlink_teardown(struct dsa_switch *ds);
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@ -168,6 +168,15 @@ static int sja1105_init_mii_settings(struct sja1105_private *priv)
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continue;
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switch (priv->phy_mode[i]) {
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case PHY_INTERFACE_MODE_INTERNAL:
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if (priv->info->internal_phy[i] == SJA1105_NO_PHY)
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goto unsupported;
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mii->xmii_mode[i] = XMII_MODE_MII;
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if (priv->info->internal_phy[i] == SJA1105_PHY_BASE_TX)
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mii->special[i] = true;
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break;
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case PHY_INTERFACE_MODE_REVMII:
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role = XMII_PHY;
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fallthrough;
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@ -3109,11 +3118,19 @@ static int sja1105_setup(struct dsa_switch *ds)
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dev_err(ds->dev, "Failed to register PTP clock: %d\n", rc);
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return rc;
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}
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rc = sja1105_mdiobus_register(ds);
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if (rc < 0) {
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dev_err(ds->dev, "Failed to register MDIO bus: %pe\n",
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ERR_PTR(rc));
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goto out_ptp_clock_unregister;
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}
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/* Create and send configuration down to device */
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rc = sja1105_static_config_load(priv);
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if (rc < 0) {
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dev_err(ds->dev, "Failed to load static config: %d\n", rc);
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goto out_ptp_clock_unregister;
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goto out_mdiobus_unregister;
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}
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/* Configure the CGU (PHY link modes and speeds) */
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rc = priv->info->clocking_setup(priv);
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@ -3156,6 +3173,8 @@ static int sja1105_setup(struct dsa_switch *ds)
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out_devlink_teardown:
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sja1105_devlink_teardown(ds);
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out_mdiobus_unregister:
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sja1105_mdiobus_unregister(ds);
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out_ptp_clock_unregister:
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sja1105_ptp_clock_unregister(ds);
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out_static_config_free:
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288
drivers/net/dsa/sja1105/sja1105_mdio.c
Normal file
288
drivers/net/dsa/sja1105/sja1105_mdio.c
Normal file
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@ -0,0 +1,288 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright 2021, NXP Semiconductors
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*/
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#include <linux/of_mdio.h>
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#include "sja1105.h"
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enum sja1105_mdio_opcode {
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SJA1105_C45_ADDR = 0,
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SJA1105_C22 = 1,
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SJA1105_C45_DATA = 2,
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SJA1105_C45_DATA_AUTOINC = 3,
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};
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static u64 sja1105_base_t1_encode_addr(struct sja1105_private *priv,
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int phy, enum sja1105_mdio_opcode op,
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int xad)
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{
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const struct sja1105_regs *regs = priv->info->regs;
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return regs->mdio_100base_t1 | (phy << 7) | (op << 5) | (xad << 0);
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}
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static int sja1105_base_t1_mdio_read(struct mii_bus *bus, int phy, int reg)
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{
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struct sja1105_mdio_private *mdio_priv = bus->priv;
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struct sja1105_private *priv = mdio_priv->priv;
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u64 addr;
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u32 tmp;
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int rc;
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if (reg & MII_ADDR_C45) {
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u16 mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;
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addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_ADDR,
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mmd);
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tmp = reg & MII_REGADDR_C45_MASK;
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rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
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if (rc < 0)
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return rc;
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addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_DATA,
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mmd);
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rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL);
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if (rc < 0)
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return rc;
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return tmp & 0xffff;
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}
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/* Clause 22 read */
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addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C22, reg & 0x1f);
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rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL);
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if (rc < 0)
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return rc;
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return tmp & 0xffff;
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}
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static int sja1105_base_t1_mdio_write(struct mii_bus *bus, int phy, int reg,
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u16 val)
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{
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struct sja1105_mdio_private *mdio_priv = bus->priv;
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struct sja1105_private *priv = mdio_priv->priv;
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u64 addr;
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u32 tmp;
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int rc;
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if (reg & MII_ADDR_C45) {
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u16 mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;
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addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_ADDR,
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mmd);
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tmp = reg & MII_REGADDR_C45_MASK;
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rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
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if (rc < 0)
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return rc;
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addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_DATA,
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mmd);
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tmp = val & 0xffff;
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rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
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if (rc < 0)
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return rc;
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return 0;
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}
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/* Clause 22 write */
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addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C22, reg & 0x1f);
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tmp = val & 0xffff;
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return sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
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}
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static int sja1105_base_tx_mdio_read(struct mii_bus *bus, int phy, int reg)
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{
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struct sja1105_mdio_private *mdio_priv = bus->priv;
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struct sja1105_private *priv = mdio_priv->priv;
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const struct sja1105_regs *regs = priv->info->regs;
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u32 tmp;
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int rc;
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rc = sja1105_xfer_u32(priv, SPI_READ, regs->mdio_100base_tx + reg,
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&tmp, NULL);
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if (rc < 0)
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return rc;
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return tmp & 0xffff;
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}
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static int sja1105_base_tx_mdio_write(struct mii_bus *bus, int phy, int reg,
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u16 val)
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{
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struct sja1105_mdio_private *mdio_priv = bus->priv;
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struct sja1105_private *priv = mdio_priv->priv;
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const struct sja1105_regs *regs = priv->info->regs;
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u32 tmp = val;
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return sja1105_xfer_u32(priv, SPI_WRITE, regs->mdio_100base_tx + reg,
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&tmp, NULL);
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}
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static int sja1105_mdiobus_base_tx_register(struct sja1105_private *priv,
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struct device_node *mdio_node)
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{
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struct sja1105_mdio_private *mdio_priv;
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struct device_node *np;
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struct mii_bus *bus;
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int rc = 0;
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np = of_find_compatible_node(mdio_node, NULL,
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"nxp,sja1110-base-tx-mdio");
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if (!np)
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return 0;
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if (!of_device_is_available(np))
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goto out_put_np;
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bus = mdiobus_alloc_size(sizeof(*mdio_priv));
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if (!bus) {
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rc = -ENOMEM;
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goto out_put_np;
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}
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bus->name = "SJA1110 100base-TX MDIO bus";
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snprintf(bus->id, MII_BUS_ID_SIZE, "%s-base-tx",
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dev_name(priv->ds->dev));
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bus->read = sja1105_base_tx_mdio_read;
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bus->write = sja1105_base_tx_mdio_write;
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bus->parent = priv->ds->dev;
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mdio_priv = bus->priv;
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mdio_priv->priv = priv;
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rc = of_mdiobus_register(bus, np);
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if (rc) {
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mdiobus_free(bus);
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goto out_put_np;
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}
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priv->mdio_base_tx = bus;
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out_put_np:
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of_node_put(np);
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return 0;
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}
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static void sja1105_mdiobus_base_tx_unregister(struct sja1105_private *priv)
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{
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if (!priv->mdio_base_tx)
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return;
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mdiobus_unregister(priv->mdio_base_tx);
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mdiobus_free(priv->mdio_base_tx);
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priv->mdio_base_tx = NULL;
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}
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static int sja1105_mdiobus_base_t1_register(struct sja1105_private *priv,
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struct device_node *mdio_node)
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{
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struct sja1105_mdio_private *mdio_priv;
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struct device_node *np;
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struct mii_bus *bus;
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int rc = 0;
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np = of_find_compatible_node(mdio_node, NULL,
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"nxp,sja1110-base-t1-mdio");
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if (!np)
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return 0;
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if (!of_device_is_available(np))
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goto out_put_np;
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bus = mdiobus_alloc_size(sizeof(*mdio_priv));
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if (!bus) {
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rc = -ENOMEM;
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goto out_put_np;
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}
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bus->name = "SJA1110 100base-T1 MDIO bus";
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snprintf(bus->id, MII_BUS_ID_SIZE, "%s-base-t1",
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dev_name(priv->ds->dev));
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bus->read = sja1105_base_t1_mdio_read;
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bus->write = sja1105_base_t1_mdio_write;
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bus->parent = priv->ds->dev;
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mdio_priv = bus->priv;
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mdio_priv->priv = priv;
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rc = of_mdiobus_register(bus, np);
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if (rc) {
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mdiobus_free(bus);
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goto out_put_np;
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}
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priv->mdio_base_t1 = bus;
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out_put_np:
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of_node_put(np);
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return rc;
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}
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static void sja1105_mdiobus_base_t1_unregister(struct sja1105_private *priv)
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{
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if (!priv->mdio_base_t1)
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return;
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mdiobus_unregister(priv->mdio_base_t1);
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mdiobus_free(priv->mdio_base_t1);
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priv->mdio_base_t1 = NULL;
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}
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int sja1105_mdiobus_register(struct dsa_switch *ds)
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{
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struct sja1105_private *priv = ds->priv;
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const struct sja1105_regs *regs = priv->info->regs;
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struct device_node *switch_node = ds->dev->of_node;
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struct device_node *mdio_node;
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int rc;
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mdio_node = of_get_child_by_name(switch_node, "mdios");
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if (!mdio_node)
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return 0;
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if (!of_device_is_available(mdio_node))
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goto out_put_mdio_node;
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if (regs->mdio_100base_tx != SJA1105_RSV_ADDR) {
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rc = sja1105_mdiobus_base_tx_register(priv, mdio_node);
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if (rc)
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goto err_put_mdio_node;
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}
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if (regs->mdio_100base_t1 != SJA1105_RSV_ADDR) {
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rc = sja1105_mdiobus_base_t1_register(priv, mdio_node);
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if (rc)
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goto err_free_base_tx_mdiobus;
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}
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out_put_mdio_node:
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of_node_put(mdio_node);
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return 0;
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err_free_base_tx_mdiobus:
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sja1105_mdiobus_base_tx_unregister(priv);
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err_put_mdio_node:
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of_node_put(mdio_node);
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return rc;
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}
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void sja1105_mdiobus_unregister(struct dsa_switch *ds)
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{
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struct sja1105_private *priv = ds->priv;
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sja1105_mdiobus_base_t1_unregister(priv);
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sja1105_mdiobus_base_tx_unregister(priv);
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}
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@ -436,6 +436,8 @@ static struct sja1105_regs sja1105et_regs = {
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.ptpclkval = 0x18, /* Spans 0x18 to 0x19 */
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.ptpclkrate = 0x1A,
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.ptpclkcorp = 0x1D,
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.mdio_100base_tx = SJA1105_RSV_ADDR,
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.mdio_100base_t1 = SJA1105_RSV_ADDR,
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};
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static struct sja1105_regs sja1105pqrs_regs = {
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@ -473,6 +475,8 @@ static struct sja1105_regs sja1105pqrs_regs = {
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.ptpclkrate = 0x1B,
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.ptpclkcorp = 0x1E,
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.ptpsyncts = 0x1F,
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.mdio_100base_tx = SJA1105_RSV_ADDR,
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.mdio_100base_t1 = SJA1105_RSV_ADDR,
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};
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static struct sja1105_regs sja1110_regs = {
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@ -555,6 +559,8 @@ static struct sja1105_regs sja1110_regs = {
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.ptpclkrate = SJA1110_SPI_ADDR(0x74),
|
||||
.ptpclkcorp = SJA1110_SPI_ADDR(0x80),
|
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.ptpsyncts = SJA1110_SPI_ADDR(0x84),
|
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.mdio_100base_tx = 0x1c2400,
|
||||
.mdio_100base_t1 = 0x1c1000,
|
||||
};
|
||||
|
||||
const struct sja1105_info sja1105e_info = {
|
||||
|
|
@ -785,6 +791,12 @@ const struct sja1105_info sja1110a_info = {
|
|||
false, false, false, false, false, false},
|
||||
.supports_2500basex = {false, false, false, true, true,
|
||||
false, false, false, false, false, false},
|
||||
.internal_phy = {SJA1105_NO_PHY, SJA1105_PHY_BASE_TX,
|
||||
SJA1105_NO_PHY, SJA1105_NO_PHY,
|
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SJA1105_NO_PHY, SJA1105_PHY_BASE_T1,
|
||||
SJA1105_PHY_BASE_T1, SJA1105_PHY_BASE_T1,
|
||||
SJA1105_PHY_BASE_T1, SJA1105_PHY_BASE_T1,
|
||||
SJA1105_PHY_BASE_T1},
|
||||
.name = "SJA1110A",
|
||||
};
|
||||
|
||||
|
|
@ -824,6 +836,12 @@ const struct sja1105_info sja1110b_info = {
|
|||
false, false, false, false, false, false},
|
||||
.supports_2500basex = {false, false, false, true, true,
|
||||
false, false, false, false, false, false},
|
||||
.internal_phy = {SJA1105_NO_PHY, SJA1105_PHY_BASE_TX,
|
||||
SJA1105_NO_PHY, SJA1105_NO_PHY,
|
||||
SJA1105_NO_PHY, SJA1105_PHY_BASE_T1,
|
||||
SJA1105_PHY_BASE_T1, SJA1105_PHY_BASE_T1,
|
||||
SJA1105_PHY_BASE_T1, SJA1105_PHY_BASE_T1,
|
||||
SJA1105_NO_PHY},
|
||||
.name = "SJA1110B",
|
||||
};
|
||||
|
||||
|
|
@ -863,6 +881,12 @@ const struct sja1105_info sja1110c_info = {
|
|||
false, false, false, false, false, false},
|
||||
.supports_2500basex = {false, false, false, false, true,
|
||||
false, false, false, false, false, false},
|
||||
.internal_phy = {SJA1105_NO_PHY, SJA1105_PHY_BASE_TX,
|
||||
SJA1105_NO_PHY, SJA1105_NO_PHY,
|
||||
SJA1105_NO_PHY, SJA1105_PHY_BASE_T1,
|
||||
SJA1105_PHY_BASE_T1, SJA1105_PHY_BASE_T1,
|
||||
SJA1105_NO_PHY, SJA1105_NO_PHY,
|
||||
SJA1105_NO_PHY},
|
||||
.name = "SJA1110C",
|
||||
};
|
||||
|
||||
|
|
@ -900,5 +924,11 @@ const struct sja1105_info sja1110d_info = {
|
|||
false, false, false, false, false, false},
|
||||
.supports_sgmii = {false, true, true, true, true,
|
||||
false, false, false, false, false, false},
|
||||
.internal_phy = {SJA1105_NO_PHY, SJA1105_NO_PHY,
|
||||
SJA1105_NO_PHY, SJA1105_NO_PHY,
|
||||
SJA1105_NO_PHY, SJA1105_PHY_BASE_T1,
|
||||
SJA1105_PHY_BASE_T1, SJA1105_PHY_BASE_T1,
|
||||
SJA1105_NO_PHY, SJA1105_NO_PHY,
|
||||
SJA1105_NO_PHY},
|
||||
.name = "SJA1110D",
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue