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	x86: KVM: Advertise AVX-IFMA CPUID to user space
AVX-IFMA is a new instruction in the latest Intel platform Sierra Forest. This instruction packed multiplies unsigned 52-bit integers and adds the low/high 52-bit products to Qword Accumulators. The bit definition: CPUID.(EAX=7,ECX=1):EAX[bit 23] AVX-IFMA is on an expected-dense CPUID leaf and some other bits on this leaf have kernel usages. Given that, define this feature bit like X86_FEATURE_<name> in kernel. Considering AVX-IFMA itself has no truly kernel usages and /proc/cpuinfo has too much unreadable flags, hide this one in /proc/cpuinfo. Advertise AVX-IFMA to KVM userspace. This is safe because there are no new VMX controls or additional host enabling required for guests to use this feature. Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com> Acked-by: Borislav Petkov <bp@suse.de> Message-Id: <20221125125845.1182922-6-jiaxi.chen@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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					@ -310,6 +310,7 @@
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#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
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					#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
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#define X86_FEATURE_CMPCCXADD           (12*32+ 7) /* "" CMPccXADD instructions */
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					#define X86_FEATURE_CMPCCXADD           (12*32+ 7) /* "" CMPccXADD instructions */
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#define X86_FEATURE_AMX_FP16		(12*32+21) /* "" AMX fp16 Support */
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					#define X86_FEATURE_AMX_FP16		(12*32+21) /* "" AMX fp16 Support */
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					#define X86_FEATURE_AVX_IFMA            (12*32+23) /* "" Support for VPMADD52[H,L]UQ */
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/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
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					/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
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#define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
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					#define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
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					@ -663,7 +663,8 @@ void kvm_set_cpu_caps(void)
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		kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
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							kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
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	kvm_cpu_cap_mask(CPUID_7_1_EAX,
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						kvm_cpu_cap_mask(CPUID_7_1_EAX,
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		F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | F(AMX_FP16)
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							F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | F(AMX_FP16) |
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							F(AVX_IFMA)
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	);
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						);
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	kvm_cpu_cap_mask(CPUID_D_1_EAX,
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						kvm_cpu_cap_mask(CPUID_D_1_EAX,
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