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gpio: Add Avionic Design N-bit GPIO expander support
This commit adds a driver for the Avionic Design N-bit GPIO expander. The expander provides a variable number of GPIO pins with interrupt support. Changes in v2: - allow building the driver as a module - assign of_node unconditionally - use linear mapping IRQ domain - properly cleanup IRQ domain - add OF device table and annotate device tables - emulate rising and falling edge triggers - increase #gpio-cells to 2 - drop support for !OF - use IS_ENABLED to conditionalize DEBUG_FS code Changes in v3: - make IRQ support runtime configurable (interrupt-controller property) - drop interrupt-controller and #interrupt-cells from DT binding - add inline to_adnp() function to wrap container_of() macro - consistently use adnp as name for struct adnp variables - remove irq_mask_cur and rename irq_mask to irq_enable - fix a subtle deadlock in adnp_gpio_direction_output() - remove dynamic allocations from debugfs code - rename regs to num_regs to avoid confusion - annotate non-trivial code with comments - don't acquire mutex in adnp_gpio_get() - assume NO_IRQ == 0 Cc: Grant Likely <grant.likely@secretlab.ca> Cc: devicetree-discuss@lists.ozlabs.org Cc: Linus Walleij <linus.walleij@stericsson.com> Cc: linux-kernel@vger.kernel.org Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Thierry Reding
Linus Walleij
parent
d724f1c9c3
commit
5e969a401a
4 changed files with 653 additions and 0 deletions
30
Documentation/devicetree/bindings/gpio/gpio-adnp.txt
Normal file
30
Documentation/devicetree/bindings/gpio/gpio-adnp.txt
Normal file
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@ -0,0 +1,30 @@
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Avionic Design N-bit GPIO expander bindings
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Required properties:
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- compatible: should be "ad,gpio-adnp"
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- reg: The I2C slave address for this device.
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- interrupt-parent: phandle of the parent interrupt controller.
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- interrupts: Interrupt specifier for the controllers interrupt.
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- #gpio-cells: Should be 2. The first cell is the GPIO number and the
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second cell is used to specify optional parameters:
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- bit 0: polarity (0: normal, 1: inverted)
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- gpio-controller: Marks the device as a GPIO controller
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- nr-gpios: The number of pins supported by the controller.
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Example:
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gpioext: gpio-controller@41 {
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compatible = "ad,gpio-adnp";
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reg = <0x41>;
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interrupt-parent = <&gpio>;
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interrupts = <160 1>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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nr-gpios = <64>;
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};
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@ -444,6 +444,17 @@ config GPIO_ADP5588_IRQ
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Say yes here to enable the adp5588 to be used as an interrupt
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controller. It requires the driver to be built in the kernel.
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config GPIO_ADNP
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tristate "Avionic Design N-bit GPIO expander"
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depends on I2C && OF
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help
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This option enables support for N GPIOs found on Avionic Design
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I2C GPIO expanders. The register space will be extended by powers
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of two, so the controller will need to accomodate for that. For
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example: if a controller provides 48 pins, 6 registers will be
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enough to represent all pins, but the driver will assume a
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register layout for 64 pins (8 registers).
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comment "PCI GPIO expanders:"
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config GPIO_CS5535
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@ -10,6 +10,7 @@ obj-$(CONFIG_GPIO_GENERIC) += gpio-generic.o
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obj-$(CONFIG_GPIO_74X164) += gpio-74x164.o
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obj-$(CONFIG_GPIO_AB8500) += gpio-ab8500.o
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obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o
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obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o
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obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o
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obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
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611
drivers/gpio/gpio-adnp.c
Normal file
611
drivers/gpio/gpio-adnp.c
Normal file
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@ -0,0 +1,611 @@
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/*
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* Copyright (C) 2011-2012 Avionic Design GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/gpio.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of_irq.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift)
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#define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift)
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#define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift)
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#define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift)
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#define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift)
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struct adnp {
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struct i2c_client *client;
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struct gpio_chip gpio;
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unsigned int reg_shift;
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struct mutex i2c_lock;
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struct irq_domain *domain;
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struct mutex irq_lock;
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u8 *irq_enable;
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u8 *irq_level;
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u8 *irq_rise;
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u8 *irq_fall;
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u8 *irq_high;
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u8 *irq_low;
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};
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static inline struct adnp *to_adnp(struct gpio_chip *chip)
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{
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return container_of(chip, struct adnp, gpio);
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}
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static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value)
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{
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int err;
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err = i2c_smbus_read_byte_data(adnp->client, offset);
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if (err < 0) {
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dev_err(adnp->gpio.dev, "%s failed: %d\n",
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"i2c_smbus_read_byte_data()", err);
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return err;
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}
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*value = err;
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return 0;
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}
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static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value)
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{
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int err;
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err = i2c_smbus_write_byte_data(adnp->client, offset, value);
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if (err < 0) {
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dev_err(adnp->gpio.dev, "%s failed: %d\n",
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"i2c_smbus_write_byte_data()", err);
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return err;
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}
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return 0;
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}
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static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct adnp *adnp = to_adnp(chip);
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unsigned int reg = offset >> adnp->reg_shift;
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unsigned int pos = offset & 7;
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u8 value;
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int err;
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err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value);
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if (err < 0)
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return err;
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return (value & BIT(pos)) ? 1 : 0;
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}
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static void __adnp_gpio_set(struct adnp *adnp, unsigned offset, int value)
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{
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unsigned int reg = offset >> adnp->reg_shift;
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unsigned int pos = offset & 7;
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int err;
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u8 val;
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err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val);
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if (err < 0)
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return;
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if (value)
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val |= BIT(pos);
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else
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val &= ~BIT(pos);
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adnp_write(adnp, GPIO_PLR(adnp) + reg, val);
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}
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static void adnp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct adnp *adnp = to_adnp(chip);
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mutex_lock(&adnp->i2c_lock);
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__adnp_gpio_set(adnp, offset, value);
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mutex_unlock(&adnp->i2c_lock);
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}
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static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct adnp *adnp = to_adnp(chip);
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unsigned int reg = offset >> adnp->reg_shift;
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unsigned int pos = offset & 7;
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u8 value;
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int err;
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mutex_lock(&adnp->i2c_lock);
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err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
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if (err < 0)
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goto out;
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value &= ~BIT(pos);
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err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value);
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if (err < 0)
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goto out;
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err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
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if (err < 0)
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goto out;
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if (err & BIT(pos))
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err = -EACCES;
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err = 0;
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out:
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mutex_unlock(&adnp->i2c_lock);
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return err;
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}
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static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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struct adnp *adnp = to_adnp(chip);
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unsigned int reg = offset >> adnp->reg_shift;
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unsigned int pos = offset & 7;
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int err;
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u8 val;
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mutex_lock(&adnp->i2c_lock);
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err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
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if (err < 0)
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goto out;
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val |= BIT(pos);
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err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val);
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if (err < 0)
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goto out;
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err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
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if (err < 0)
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goto out;
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if (!(val & BIT(pos))) {
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err = -EPERM;
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goto out;
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}
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__adnp_gpio_set(adnp, offset, value);
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err = 0;
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out:
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mutex_unlock(&adnp->i2c_lock);
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return err;
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}
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static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
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{
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struct adnp *adnp = to_adnp(chip);
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unsigned int num_regs = 1 << adnp->reg_shift, i, j;
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int err;
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for (i = 0; i < num_regs; i++) {
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u8 ddr, plr, ier, isr;
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mutex_lock(&adnp->i2c_lock);
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err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr);
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if (err < 0) {
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mutex_unlock(&adnp->i2c_lock);
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return;
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}
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err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr);
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if (err < 0) {
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mutex_unlock(&adnp->i2c_lock);
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return;
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}
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err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
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if (err < 0) {
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mutex_unlock(&adnp->i2c_lock);
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return;
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}
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err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
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if (err < 0) {
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mutex_unlock(&adnp->i2c_lock);
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return;
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}
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mutex_unlock(&adnp->i2c_lock);
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for (j = 0; j < 8; j++) {
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unsigned int bit = (i << adnp->reg_shift) + j;
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const char *direction = "input ";
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const char *level = "low ";
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const char *interrupt = "disabled";
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const char *pending = "";
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if (ddr & BIT(j))
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direction = "output";
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if (plr & BIT(j))
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level = "high";
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if (ier & BIT(j))
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interrupt = "enabled ";
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if (isr & BIT(j))
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pending = "pending";
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seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit,
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direction, level, interrupt, pending);
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}
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}
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}
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static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios)
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{
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struct gpio_chip *chip = &adnp->gpio;
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adnp->reg_shift = get_count_order(num_gpios) - 3;
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chip->direction_input = adnp_gpio_direction_input;
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chip->direction_output = adnp_gpio_direction_output;
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chip->get = adnp_gpio_get;
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chip->set = adnp_gpio_set;
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chip->can_sleep = 1;
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if (IS_ENABLED(CONFIG_DEBUG_FS))
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chip->dbg_show = adnp_gpio_dbg_show;
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chip->base = -1;
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chip->ngpio = num_gpios;
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chip->label = adnp->client->name;
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chip->dev = &adnp->client->dev;
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chip->of_node = chip->dev->of_node;
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chip->owner = THIS_MODULE;
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return 0;
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}
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static irqreturn_t adnp_irq(int irq, void *data)
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{
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struct adnp *adnp = data;
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unsigned int num_regs, i;
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num_regs = 1 << adnp->reg_shift;
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for (i = 0; i < num_regs; i++) {
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unsigned int base = i << adnp->reg_shift, bit;
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u8 changed, level, isr, ier;
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unsigned long pending;
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int err;
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mutex_lock(&adnp->i2c_lock);
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err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level);
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if (err < 0) {
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mutex_unlock(&adnp->i2c_lock);
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continue;
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}
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err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
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if (err < 0) {
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mutex_unlock(&adnp->i2c_lock);
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continue;
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}
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err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
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if (err < 0) {
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mutex_unlock(&adnp->i2c_lock);
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continue;
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}
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mutex_unlock(&adnp->i2c_lock);
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/* determine pins that changed levels */
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changed = level ^ adnp->irq_level[i];
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/* compute edge-triggered interrupts */
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pending = changed & ((adnp->irq_fall[i] & ~level) |
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(adnp->irq_rise[i] & level));
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/* add in level-triggered interrupts */
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pending |= (adnp->irq_high[i] & level) |
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(adnp->irq_low[i] & ~level);
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/* mask out non-pending and disabled interrupts */
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pending &= isr & ier;
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for_each_set_bit(bit, &pending, 8) {
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unsigned int virq;
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virq = irq_find_mapping(adnp->domain, base + bit);
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handle_nested_irq(virq);
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}
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}
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return IRQ_HANDLED;
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}
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static int adnp_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct adnp *adnp = to_adnp(chip);
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return irq_create_mapping(adnp->domain, offset);
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}
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static void adnp_irq_mask(struct irq_data *data)
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{
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struct adnp *adnp = irq_data_get_irq_chip_data(data);
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unsigned int reg = data->hwirq >> adnp->reg_shift;
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unsigned int pos = data->hwirq & 7;
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adnp->irq_enable[reg] &= ~BIT(pos);
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}
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static void adnp_irq_unmask(struct irq_data *data)
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{
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struct adnp *adnp = irq_data_get_irq_chip_data(data);
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unsigned int reg = data->hwirq >> adnp->reg_shift;
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unsigned int pos = data->hwirq & 7;
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adnp->irq_enable[reg] |= BIT(pos);
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}
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static int adnp_irq_set_type(struct irq_data *data, unsigned int type)
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{
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struct adnp *adnp = irq_data_get_irq_chip_data(data);
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unsigned int reg = data->hwirq >> adnp->reg_shift;
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unsigned int pos = data->hwirq & 7;
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if (type & IRQ_TYPE_EDGE_RISING)
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adnp->irq_rise[reg] |= BIT(pos);
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else
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adnp->irq_rise[reg] &= ~BIT(pos);
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if (type & IRQ_TYPE_EDGE_FALLING)
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adnp->irq_fall[reg] |= BIT(pos);
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else
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adnp->irq_fall[reg] &= ~BIT(pos);
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if (type & IRQ_TYPE_LEVEL_HIGH)
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adnp->irq_high[reg] |= BIT(pos);
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else
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adnp->irq_high[reg] &= ~BIT(pos);
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if (type & IRQ_TYPE_LEVEL_LOW)
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adnp->irq_low[reg] |= BIT(pos);
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else
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adnp->irq_low[reg] &= ~BIT(pos);
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return 0;
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}
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static void adnp_irq_bus_lock(struct irq_data *data)
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{
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struct adnp *adnp = irq_data_get_irq_chip_data(data);
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mutex_lock(&adnp->irq_lock);
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}
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static void adnp_irq_bus_unlock(struct irq_data *data)
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{
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struct adnp *adnp = irq_data_get_irq_chip_data(data);
|
||||
unsigned int num_regs = 1 << adnp->reg_shift, i;
|
||||
|
||||
mutex_lock(&adnp->i2c_lock);
|
||||
|
||||
for (i = 0; i < num_regs; i++)
|
||||
adnp_write(adnp, GPIO_IER(adnp) + i, adnp->irq_enable[i]);
|
||||
|
||||
mutex_unlock(&adnp->i2c_lock);
|
||||
mutex_unlock(&adnp->irq_lock);
|
||||
}
|
||||
|
||||
static struct irq_chip adnp_irq_chip = {
|
||||
.name = "gpio-adnp",
|
||||
.irq_mask = adnp_irq_mask,
|
||||
.irq_unmask = adnp_irq_unmask,
|
||||
.irq_set_type = adnp_irq_set_type,
|
||||
.irq_bus_lock = adnp_irq_bus_lock,
|
||||
.irq_bus_sync_unlock = adnp_irq_bus_unlock,
|
||||
};
|
||||
|
||||
static int adnp_irq_map(struct irq_domain *domain, unsigned int irq,
|
||||
irq_hw_number_t hwirq)
|
||||
{
|
||||
irq_set_chip_data(irq, domain->host_data);
|
||||
irq_set_chip(irq, &adnp_irq_chip);
|
||||
irq_set_nested_thread(irq, true);
|
||||
|
||||
#ifdef CONFIG_ARM
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
#else
|
||||
irq_set_noprobe(irq);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops adnp_irq_domain_ops = {
|
||||
.map = adnp_irq_map,
|
||||
.xlate = irq_domain_xlate_twocell,
|
||||
};
|
||||
|
||||
static int adnp_irq_setup(struct adnp *adnp)
|
||||
{
|
||||
unsigned int num_regs = 1 << adnp->reg_shift, i;
|
||||
struct gpio_chip *chip = &adnp->gpio;
|
||||
int err;
|
||||
|
||||
mutex_init(&adnp->irq_lock);
|
||||
|
||||
/*
|
||||
* Allocate memory to keep track of the current level and trigger
|
||||
* modes of the interrupts. To avoid multiple allocations, a single
|
||||
* large buffer is allocated and pointers are setup to point at the
|
||||
* corresponding offsets. For consistency, the layout of the buffer
|
||||
* is chosen to match the register layout of the hardware in that
|
||||
* each segment contains the corresponding bits for all interrupts.
|
||||
*/
|
||||
adnp->irq_enable = devm_kzalloc(chip->dev, num_regs * 6, GFP_KERNEL);
|
||||
if (!adnp->irq_enable)
|
||||
return -ENOMEM;
|
||||
|
||||
adnp->irq_level = adnp->irq_enable + (num_regs * 1);
|
||||
adnp->irq_rise = adnp->irq_enable + (num_regs * 2);
|
||||
adnp->irq_fall = adnp->irq_enable + (num_regs * 3);
|
||||
adnp->irq_high = adnp->irq_enable + (num_regs * 4);
|
||||
adnp->irq_low = adnp->irq_enable + (num_regs * 5);
|
||||
|
||||
for (i = 0; i < num_regs; i++) {
|
||||
/*
|
||||
* Read the initial level of all pins to allow the emulation
|
||||
* of edge triggered interrupts.
|
||||
*/
|
||||
err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
/* disable all interrupts */
|
||||
err = adnp_write(adnp, GPIO_IER(adnp) + i, 0);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
adnp->irq_enable[i] = 0x00;
|
||||
}
|
||||
|
||||
adnp->domain = irq_domain_add_linear(chip->of_node, chip->ngpio,
|
||||
&adnp_irq_domain_ops, adnp);
|
||||
|
||||
err = request_threaded_irq(adnp->client->irq, NULL, adnp_irq,
|
||||
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
|
||||
dev_name(chip->dev), adnp);
|
||||
if (err != 0) {
|
||||
dev_err(chip->dev, "can't request IRQ#%d: %d\n",
|
||||
adnp->client->irq, err);
|
||||
goto error;
|
||||
}
|
||||
|
||||
chip->to_irq = adnp_gpio_to_irq;
|
||||
return 0;
|
||||
|
||||
error:
|
||||
irq_domain_remove(adnp->domain);
|
||||
return err;
|
||||
}
|
||||
|
||||
static void adnp_irq_teardown(struct adnp *adnp)
|
||||
{
|
||||
unsigned int irq, i;
|
||||
|
||||
free_irq(adnp->client->irq, adnp);
|
||||
|
||||
for (i = 0; i < adnp->gpio.ngpio; i++) {
|
||||
irq = irq_find_mapping(adnp->domain, i);
|
||||
if (irq > 0)
|
||||
irq_dispose_mapping(irq);
|
||||
}
|
||||
|
||||
irq_domain_remove(adnp->domain);
|
||||
}
|
||||
|
||||
static __devinit int adnp_i2c_probe(struct i2c_client *client,
|
||||
const struct i2c_device_id *id)
|
||||
{
|
||||
struct device_node *np = client->dev.of_node;
|
||||
struct adnp *adnp;
|
||||
u32 num_gpios;
|
||||
int err;
|
||||
|
||||
err = of_property_read_u32(np, "nr-gpios", &num_gpios);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
client->irq = irq_of_parse_and_map(np, 0);
|
||||
if (!client->irq)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL);
|
||||
if (!adnp)
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_init(&adnp->i2c_lock);
|
||||
adnp->client = client;
|
||||
|
||||
err = adnp_gpio_setup(adnp, num_gpios);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
if (of_find_property(np, "interrupt-controller", NULL)) {
|
||||
err = adnp_irq_setup(adnp);
|
||||
if (err < 0)
|
||||
goto teardown;
|
||||
}
|
||||
|
||||
err = gpiochip_add(&adnp->gpio);
|
||||
if (err < 0)
|
||||
goto teardown;
|
||||
|
||||
i2c_set_clientdata(client, adnp);
|
||||
return 0;
|
||||
|
||||
teardown:
|
||||
if (of_find_property(np, "interrupt-controller", NULL))
|
||||
adnp_irq_teardown(adnp);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static __devexit int adnp_i2c_remove(struct i2c_client *client)
|
||||
{
|
||||
struct adnp *adnp = i2c_get_clientdata(client);
|
||||
struct device_node *np = client->dev.of_node;
|
||||
int err;
|
||||
|
||||
err = gpiochip_remove(&adnp->gpio);
|
||||
if (err < 0) {
|
||||
dev_err(&client->dev, "%s failed: %d\n", "gpiochip_remove()",
|
||||
err);
|
||||
return err;
|
||||
}
|
||||
|
||||
if (of_find_property(np, "interrupt-controller", NULL))
|
||||
adnp_irq_teardown(adnp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct i2c_device_id adnp_i2c_id[] __devinitconst = {
|
||||
{ "gpio-adnp" },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, adnp_i2c_id);
|
||||
|
||||
static const struct of_device_id adnp_of_match[] __devinitconst = {
|
||||
{ .compatible = "ad,gpio-adnp", },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, adnp_of_match);
|
||||
|
||||
static struct i2c_driver adnp_i2c_driver = {
|
||||
.driver = {
|
||||
.name = "gpio-adnp",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(adnp_of_match),
|
||||
},
|
||||
.probe = adnp_i2c_probe,
|
||||
.remove = __devexit_p(adnp_i2c_remove),
|
||||
.id_table = adnp_i2c_id,
|
||||
};
|
||||
module_i2c_driver(adnp_i2c_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander");
|
||||
MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in a new issue