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drm/amdgpu: add si implementation v10

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v5: rebase fixes
v6: add mgcg arrays
v7: rebase fixes
v8: rebase fixes
v9: add get_disabled_bios(), make get_xclk static
v10: fix oland and hainan asic specific handle at si_program_aspm

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ken Wang 2016-01-19 14:08:49 +08:00 committed by Alex Deucher
parent 30d1574fa4
commit 62a3755341
3 changed files with 2041 additions and 0 deletions
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1963
drivers/gpu/drm/amd/amdgpu/si.c Normal file
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33
drivers/gpu/drm/amd/amdgpu/si.h Normal file
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@ -0,0 +1,33 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __SI_H__
#define __SI_H__
extern const struct amd_ip_funcs si_common_ip_funcs;
void si_srbm_select(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 queue, u32 vmid);
int si_set_ip_blocks(struct amdgpu_device *adev);
#endif

45
drivers/gpu/drm/amd/include/asic_reg/si/sid.h
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@ -1221,6 +1221,37 @@
# define ADDR_SURF_4_BANK 1 # define ADDR_SURF_4_BANK 1
# define ADDR_SURF_8_BANK 2 # define ADDR_SURF_8_BANK 2
# define ADDR_SURF_16_BANK 3 # define ADDR_SURF_16_BANK 3
#define GB_TILE_MODE1 0x2645
#define GB_TILE_MODE2 0x2646
#define GB_TILE_MODE3 0x2647
#define GB_TILE_MODE4 0x2648
#define GB_TILE_MODE5 0x2649
#define GB_TILE_MODE6 0x264a
#define GB_TILE_MODE7 0x264b
#define GB_TILE_MODE8 0x264c
#define GB_TILE_MODE9 0x264d
#define GB_TILE_MODE10 0x264e
#define GB_TILE_MODE11 0x264f
#define GB_TILE_MODE12 0x2650
#define GB_TILE_MODE13 0x2651
#define GB_TILE_MODE14 0x2652
#define GB_TILE_MODE15 0x2653
#define GB_TILE_MODE16 0x2654
#define GB_TILE_MODE17 0x2655
#define GB_TILE_MODE18 0x2656
#define GB_TILE_MODE19 0x2657
#define GB_TILE_MODE20 0x2658
#define GB_TILE_MODE21 0x2659
#define GB_TILE_MODE22 0x265a
#define GB_TILE_MODE23 0x265b
#define GB_TILE_MODE24 0x265c
#define GB_TILE_MODE25 0x265d
#define GB_TILE_MODE26 0x265e
#define GB_TILE_MODE27 0x265f
#define GB_TILE_MODE28 0x2660
#define GB_TILE_MODE29 0x2661
#define GB_TILE_MODE30 0x2662
#define GB_TILE_MODE31 0x2663
#define CB_PERFCOUNTER0_SELECT0 0x2688 #define CB_PERFCOUNTER0_SELECT0 0x2688
#define CB_PERFCOUNTER0_SELECT1 0x2689 #define CB_PERFCOUNTER0_SELECT1 0x2689
@ -2017,8 +2048,22 @@
#define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0) #define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)
#define AVIVO_D1VGA_CONTROL 0x00cc #define AVIVO_D1VGA_CONTROL 0x00cc
# define AVIVO_DVGA_CONTROL_MODE_ENABLE (1 << 0)
# define AVIVO_DVGA_CONTROL_TIMING_SELECT (1 << 8)
# define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9)
# define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10)
# define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16)
# define AVIVO_DVGA_CONTROL_ROTATE (1 << 24)
#define AVIVO_D2VGA_CONTROL 0x00ce #define AVIVO_D2VGA_CONTROL 0x00ce
#define R600_BUS_CNTL 0x1508
# define R600_BIOS_ROM_DIS (1 << 1)
#define R600_ROM_CNTL 0x580
# define R600_SCK_OVERWRITE (1 << 1)
# define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
# define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28)
#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1 #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1
#define FMT_BIT_DEPTH_CONTROL 0x1bf2 #define FMT_BIT_DEPTH_CONTROL 0x1bf2