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drm/rockchip: dw_hdmi: switch to FIELD_PREP_WM16* macros
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those drivers that use constant masks. Remove this driver's very own HIWORD_UPDATE macro, and replace all instances of it with equivalent instantiations of FIELD_PREP_WM16 or FIELD_PREP_WM16_CONST, depending on whether it's in an initializer. This gives us better error checking, and a centrally agreed upon signature for this macro, to ease in code comprehension. Because FIELD_PREP_WM16/FIELD_PREP_WM16_CONST shifts the value to the mask (like FIELD_PREP et al do), a lot of macro instantiations get easier to read. This was tested on an RK3568 ODROID M1, as well as an RK3399 ROCKPro64. Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Tested-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
This commit is contained in:
Nicolas Frattaroli
Yury Norov
parent
a104de64bf
commit
63df37f3fc
1 changed files with 35 additions and 43 deletions
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@ -4,6 +4,7 @@
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*/
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#include <linux/clk.h>
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#include <linux/hw_bitfield.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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@ -54,8 +55,6 @@
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#define RK3568_HDMI_SDAIN_MSK BIT(15)
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#define RK3568_HDMI_SCLIN_MSK BIT(14)
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#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
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/**
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* struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
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* @lcdsel_grf_reg: grf register offset of lcdc select
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@ -355,17 +354,14 @@ static void dw_hdmi_rk3228_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)
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dw_hdmi_phy_setup_hpd(dw_hdmi, data);
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regmap_write(hdmi->regmap,
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RK3228_GRF_SOC_CON6,
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HIWORD_UPDATE(RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |
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RK3228_HDMI_SCL_VSEL,
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RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |
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RK3228_HDMI_SCL_VSEL));
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regmap_write(hdmi->regmap, RK3228_GRF_SOC_CON6,
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FIELD_PREP_WM16(RK3228_HDMI_HPD_VSEL, 1) |
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FIELD_PREP_WM16(RK3228_HDMI_SDA_VSEL, 1) |
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FIELD_PREP_WM16(RK3228_HDMI_SCL_VSEL, 1));
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regmap_write(hdmi->regmap,
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RK3228_GRF_SOC_CON2,
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HIWORD_UPDATE(RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK,
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RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK));
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regmap_write(hdmi->regmap, RK3228_GRF_SOC_CON2,
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FIELD_PREP_WM16(RK3228_HDMI_SDAIN_MSK, 1) |
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FIELD_PREP_WM16(RK3328_HDMI_SCLIN_MSK, 1));
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}
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static enum drm_connector_status
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@ -377,15 +373,13 @@ dw_hdmi_rk3328_read_hpd(struct dw_hdmi *dw_hdmi, void *data)
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status = dw_hdmi_phy_read_hpd(dw_hdmi, data);
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if (status == connector_status_connected)
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regmap_write(hdmi->regmap,
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RK3328_GRF_SOC_CON4,
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HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V,
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RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V));
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regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON4,
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FIELD_PREP_WM16(RK3328_HDMI_SDA_5V, 1) |
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FIELD_PREP_WM16(RK3328_HDMI_SCL_5V, 1));
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else
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regmap_write(hdmi->regmap,
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RK3328_GRF_SOC_CON4,
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HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V |
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RK3328_HDMI_SCL_5V));
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regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON4,
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FIELD_PREP_WM16(RK3328_HDMI_SDA_5V, 0) |
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FIELD_PREP_WM16(RK3328_HDMI_SCL_5V, 0));
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return status;
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}
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@ -396,21 +390,21 @@ static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)
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dw_hdmi_phy_setup_hpd(dw_hdmi, data);
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/* Enable and map pins to 3V grf-controlled io-voltage */
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regmap_write(hdmi->regmap,
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RK3328_GRF_SOC_CON4,
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HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V |
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RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V |
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RK3328_HDMI_HPD_5V));
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regmap_write(hdmi->regmap,
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RK3328_GRF_SOC_CON3,
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HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF |
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RK3328_HDMI_HPD5V_GRF |
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RK3328_HDMI_CEC5V_GRF));
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regmap_write(hdmi->regmap,
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RK3328_GRF_SOC_CON2,
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HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK,
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RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK |
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RK3328_HDMI_HPD_IOE));
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regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON4,
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FIELD_PREP_WM16(RK3328_HDMI_HPD_SARADC, 0) |
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FIELD_PREP_WM16(RK3328_HDMI_CEC_5V, 0) |
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FIELD_PREP_WM16(RK3328_HDMI_SDA_5V, 0) |
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FIELD_PREP_WM16(RK3328_HDMI_SCL_5V, 0) |
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FIELD_PREP_WM16(RK3328_HDMI_HPD_5V, 0));
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regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON3,
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FIELD_PREP_WM16(RK3328_HDMI_SDA5V_GRF, 0) |
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FIELD_PREP_WM16(RK3328_HDMI_SCL5V_GRF, 0) |
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FIELD_PREP_WM16(RK3328_HDMI_HPD5V_GRF, 0) |
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FIELD_PREP_WM16(RK3328_HDMI_CEC5V_GRF, 0));
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regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON2,
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FIELD_PREP_WM16(RK3328_HDMI_SDAIN_MSK, 1) |
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FIELD_PREP_WM16(RK3328_HDMI_SCLIN_MSK, 1) |
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FIELD_PREP_WM16(RK3328_HDMI_HPD_IOE, 0));
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dw_hdmi_rk3328_read_hpd(dw_hdmi, data);
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}
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@ -438,8 +432,8 @@ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
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static struct rockchip_hdmi_chip_data rk3288_chip_data = {
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.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
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.lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
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.lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL),
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.lcdsel_big = FIELD_PREP_WM16_CONST(RK3288_HDMI_LCDC_SEL, 0),
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.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_HDMI_LCDC_SEL, 1),
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.max_tmds_clock = 340000,
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};
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@ -475,8 +469,8 @@ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
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static struct rockchip_hdmi_chip_data rk3399_chip_data = {
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.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
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.lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),
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.lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL),
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.lcdsel_big = FIELD_PREP_WM16_CONST(RK3399_HDMI_LCDC_SEL, 0),
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.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3399_HDMI_LCDC_SEL, 1),
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.max_tmds_clock = 594000,
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};
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@ -589,10 +583,8 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
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if (hdmi->chip_data == &rk3568_chip_data) {
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regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
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HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
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RK3568_HDMI_SCLIN_MSK,
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RK3568_HDMI_SDAIN_MSK |
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RK3568_HDMI_SCLIN_MSK));
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FIELD_PREP_WM16(RK3568_HDMI_SDAIN_MSK, 1) |
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FIELD_PREP_WM16(RK3568_HDMI_SCLIN_MSK, 1));
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}
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drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
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