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	ath9k: do btcoex ASPM disabling at initialization time
Disable ASPM in pci ->probe on upstream (device) and downstream (PCIe port) component. According to e1000e driver authors this is required. I did not find that requirement in PCIe spec, but it seems to be logical for me. This need to be fixed for CONFIG_PCIEASPM, that will be done later ... Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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					 4 changed files with 29 additions and 29 deletions
				
			
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			@ -603,10 +603,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
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	ath9k_hw_init_mode_regs(ah);
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	if (ah->is_pciexpress)
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		ath9k_hw_aspm_init(ah);
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	else
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	if (!ah->is_pciexpress)
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		ath9k_hw_disablepcie(ah);
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	if (!AR_SREV_9300_20_OR_LATER(ah))
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			@ -621,6 +618,9 @@ static int __ath9k_hw_init(struct ath_hw *ah)
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	if (r)
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		return r;
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	if (ah->is_pciexpress)
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		ath9k_hw_aspm_init(ah);
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	r = ath9k_hw_init_macaddr(ah);
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	if (r) {
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		ath_err(common, "Failed to initialize MAC address\n");
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			@ -1036,10 +1036,6 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
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void ath9k_hw_proc_mib_event(struct ath_hw *ah);
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void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
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#define ATH_PCIE_CAP_LINK_CTRL	0x70
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#define ATH_PCIE_CAP_LINK_L0S	1
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#define ATH_PCIE_CAP_LINK_L1	2
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#define ATH9K_CLOCK_RATE_CCK		22
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#define ATH9K_CLOCK_RATE_5GHZ_OFDM	40
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#define ATH9K_CLOCK_RATE_2GHZ_OFDM	44
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			@ -1145,8 +1145,6 @@ static int ath9k_start(struct ieee80211_hw *hw)
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					   AR_STOMP_LOW_WLAN_WGHT);
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		ath9k_hw_btcoex_enable(ah);
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		if (common->bus_ops->bt_coex_prep)
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			common->bus_ops->bt_coex_prep(common);
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		if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
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			ath9k_btcoex_timer_resume(sc);
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	}
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			@ -89,23 +89,6 @@ static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
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	return true;
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}
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/*
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 * Bluetooth coexistance requires disabling ASPM.
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 */
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static void ath_pci_bt_coex_prep(struct ath_common *common)
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{
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	struct ath_softc *sc = (struct ath_softc *) common->priv;
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	struct pci_dev *pdev = to_pci_dev(sc->dev);
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	u8 aspm;
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	if (!pci_is_pcie(pdev))
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		return;
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	pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
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	aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
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	pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
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}
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static void ath_pci_extn_synch_enable(struct ath_common *common)
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{
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	struct ath_softc *sc = (struct ath_softc *) common->priv;
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			@ -117,6 +100,7 @@ static void ath_pci_extn_synch_enable(struct ath_common *common)
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	pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
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}
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/* Need to be called after we discover btcoex capabilities */
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static void ath_pci_aspm_init(struct ath_common *common)
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{
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	struct ath_softc *sc = (struct ath_softc *) common->priv;
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			@ -126,10 +110,33 @@ static void ath_pci_aspm_init(struct ath_common *common)
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	int pos;
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	u8 aspm;
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	if (!pci_is_pcie(pdev))
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	pos = pci_pcie_cap(pdev);
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	if (!pos)
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		return;
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	parent = pdev->bus->self;
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	if (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) {
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		/* Bluetooth coexistance requires disabling ASPM. */
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		pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &aspm);
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		aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
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		pci_write_config_byte(pdev, pos + PCI_EXP_LNKCTL, aspm);
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		/*
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		 * Both upstream and downstream PCIe components should
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		 * have the same ASPM settings.
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		 */
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		if (WARN_ON(!parent))
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			return;
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		pos = pci_pcie_cap(parent);
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		pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
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		aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
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		pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm);
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		return;
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	}
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	if (WARN_ON(!parent))
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		return;
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			@ -146,7 +153,6 @@ static const struct ath_bus_ops ath_pci_bus_ops = {
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	.ath_bus_type = ATH_PCI,
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	.read_cachesize = ath_pci_read_cachesize,
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	.eeprom_read = ath_pci_eeprom_read,
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	.bt_coex_prep = ath_pci_bt_coex_prep,
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	.extn_synch_en = ath_pci_extn_synch_enable,
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	.aspm_init = ath_pci_aspm_init,
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};
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