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[ARM] 5414/2: ep93xx m2p dma core
Add m2p dma support to the ep93xx Signed-off-by: Ryan Mallon <ryan@bluewatersys.com> Acked-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Ryan Mallon
Russell King
parent
1c8daabe1d
commit
6d831c6554
4 changed files with 463 additions and 2 deletions
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@ -1,7 +1,7 @@
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#
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# Makefile for the linux kernel.
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#
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obj-y := core.o clock.o gpio.o
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obj-y := core.o clock.o dma-m2p.o gpio.o
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obj-m :=
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obj-n :=
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obj- :=
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408
arch/arm/mach-ep93xx/dma-m2p.c
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408
arch/arm/mach-ep93xx/dma-m2p.c
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@ -0,0 +1,408 @@
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/*
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* arch/arm/mach-ep93xx/dma-m2p.c
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* M2P DMA handling for Cirrus EP93xx chips.
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*
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* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
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* Copyright (C) 2006 Applied Data Systems
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*
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* Copyright (C) 2009 Ryan Mallon <ryan@bluewatersys.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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/*
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* On the EP93xx chip the following peripherals my be allocated to the 10
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* Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive).
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*
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* I2S contains 3 Tx and 3 Rx DMA Channels
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* AAC contains 3 Tx and 3 Rx DMA Channels
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* UART1 contains 1 Tx and 1 Rx DMA Channels
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* UART2 contains 1 Tx and 1 Rx DMA Channels
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* UART3 contains 1 Tx and 1 Rx DMA Channels
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* IrDA contains 1 Tx and 1 Rx DMA Channels
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*
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* SSP and IDE use the Memory to Memory (M2M) channels and are not covered
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* with this implementation.
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <mach/dma.h>
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#include <mach/hardware.h>
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#define M2P_CONTROL 0x00
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#define M2P_CONTROL_STALL_IRQ_EN (1 << 0)
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#define M2P_CONTROL_NFB_IRQ_EN (1 << 1)
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#define M2P_CONTROL_ERROR_IRQ_EN (1 << 3)
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#define M2P_CONTROL_ENABLE (1 << 4)
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#define M2P_INTERRUPT 0x04
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#define M2P_INTERRUPT_STALL (1 << 0)
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#define M2P_INTERRUPT_NFB (1 << 1)
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#define M2P_INTERRUPT_ERROR (1 << 3)
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#define M2P_PPALLOC 0x08
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#define M2P_STATUS 0x0c
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#define M2P_REMAIN 0x14
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#define M2P_MAXCNT0 0x20
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#define M2P_BASE0 0x24
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#define M2P_MAXCNT1 0x30
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#define M2P_BASE1 0x34
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#define STATE_IDLE 0 /* Channel is inactive. */
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#define STATE_STALL 1 /* Channel is active, no buffers pending. */
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#define STATE_ON 2 /* Channel is active, one buffer pending. */
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#define STATE_NEXT 3 /* Channel is active, two buffers pending. */
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struct m2p_channel {
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char *name;
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void __iomem *base;
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int irq;
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struct clk *clk;
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spinlock_t lock;
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void *client;
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unsigned next_slot:1;
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struct ep93xx_dma_buffer *buffer_xfer;
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struct ep93xx_dma_buffer *buffer_next;
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struct list_head buffers_pending;
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};
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static struct m2p_channel m2p_rx[] = {
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{"m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1},
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{"m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3},
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{"m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5},
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{"m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7},
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{"m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9},
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{NULL},
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};
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static struct m2p_channel m2p_tx[] = {
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{"m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0},
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{"m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2},
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{"m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4},
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{"m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6},
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{"m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8},
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{NULL},
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};
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static void feed_buf(struct m2p_channel *ch, struct ep93xx_dma_buffer *buf)
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{
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if (ch->next_slot == 0) {
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writel(buf->size, ch->base + M2P_MAXCNT0);
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writel(buf->bus_addr, ch->base + M2P_BASE0);
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} else {
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writel(buf->size, ch->base + M2P_MAXCNT1);
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writel(buf->bus_addr, ch->base + M2P_BASE1);
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}
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ch->next_slot ^= 1;
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}
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static void choose_buffer_xfer(struct m2p_channel *ch)
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{
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struct ep93xx_dma_buffer *buf;
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ch->buffer_xfer = NULL;
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if (!list_empty(&ch->buffers_pending)) {
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buf = list_entry(ch->buffers_pending.next,
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struct ep93xx_dma_buffer, list);
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list_del(&buf->list);
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feed_buf(ch, buf);
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ch->buffer_xfer = buf;
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}
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}
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static void choose_buffer_next(struct m2p_channel *ch)
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{
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struct ep93xx_dma_buffer *buf;
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ch->buffer_next = NULL;
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if (!list_empty(&ch->buffers_pending)) {
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buf = list_entry(ch->buffers_pending.next,
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struct ep93xx_dma_buffer, list);
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list_del(&buf->list);
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feed_buf(ch, buf);
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ch->buffer_next = buf;
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}
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}
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static inline void m2p_set_control(struct m2p_channel *ch, u32 v)
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{
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/*
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* The control register must be read immediately after being written so
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* that the internal state machine is correctly updated. See the ep93xx
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* users' guide for details.
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*/
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writel(v, ch->base + M2P_CONTROL);
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readl(ch->base + M2P_CONTROL);
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}
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static inline int m2p_channel_state(struct m2p_channel *ch)
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{
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return (readl(ch->base + M2P_STATUS) >> 4) & 0x3;
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}
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static irqreturn_t m2p_irq(int irq, void *dev_id)
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{
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struct m2p_channel *ch = dev_id;
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struct ep93xx_dma_m2p_client *cl;
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u32 irq_status, v;
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int error = 0;
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cl = ch->client;
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spin_lock(&ch->lock);
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irq_status = readl(ch->base + M2P_INTERRUPT);
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if (irq_status & M2P_INTERRUPT_ERROR) {
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writel(M2P_INTERRUPT_ERROR, ch->base + M2P_INTERRUPT);
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error = 1;
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}
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if ((irq_status & (M2P_INTERRUPT_STALL | M2P_INTERRUPT_NFB)) == 0) {
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spin_unlock(&ch->lock);
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return IRQ_NONE;
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}
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switch (m2p_channel_state(ch)) {
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case STATE_IDLE:
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pr_crit("m2p_irq: dma interrupt without a dma buffer\n");
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BUG();
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break;
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case STATE_STALL:
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cl->buffer_finished(cl->cookie, ch->buffer_xfer, 0, error);
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if (ch->buffer_next != NULL) {
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cl->buffer_finished(cl->cookie, ch->buffer_next,
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0, error);
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}
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choose_buffer_xfer(ch);
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choose_buffer_next(ch);
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if (ch->buffer_xfer != NULL)
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cl->buffer_started(cl->cookie, ch->buffer_xfer);
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break;
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case STATE_ON:
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cl->buffer_finished(cl->cookie, ch->buffer_xfer, 0, error);
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ch->buffer_xfer = ch->buffer_next;
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choose_buffer_next(ch);
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cl->buffer_started(cl->cookie, ch->buffer_xfer);
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break;
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case STATE_NEXT:
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pr_crit("m2p_irq: dma interrupt while next\n");
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BUG();
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break;
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}
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v = readl(ch->base + M2P_CONTROL) & ~(M2P_CONTROL_STALL_IRQ_EN |
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M2P_CONTROL_NFB_IRQ_EN);
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if (ch->buffer_xfer != NULL)
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v |= M2P_CONTROL_STALL_IRQ_EN;
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if (ch->buffer_next != NULL)
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v |= M2P_CONTROL_NFB_IRQ_EN;
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m2p_set_control(ch, v);
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spin_unlock(&ch->lock);
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return IRQ_HANDLED;
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}
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static struct m2p_channel *find_free_channel(struct ep93xx_dma_m2p_client *cl)
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{
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struct m2p_channel *ch;
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int i;
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if (cl->flags & EP93XX_DMA_M2P_RX)
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ch = m2p_rx;
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else
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ch = m2p_tx;
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for (i = 0; ch[i].base; i++) {
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struct ep93xx_dma_m2p_client *client;
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client = ch[i].client;
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if (client != NULL) {
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int port;
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port = cl->flags & EP93XX_DMA_M2P_PORT_MASK;
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if (port == (client->flags &
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EP93XX_DMA_M2P_PORT_MASK)) {
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pr_warning("DMA channel already used by %s\n",
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cl->name ? : "unknown client");
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return ERR_PTR(-EBUSY);
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}
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}
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}
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for (i = 0; ch[i].base; i++) {
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if (ch[i].client == NULL)
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return ch + i;
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}
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pr_warning("No free DMA channel for %s\n",
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cl->name ? : "unknown client");
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return ERR_PTR(-ENODEV);
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}
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static void channel_enable(struct m2p_channel *ch)
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{
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struct ep93xx_dma_m2p_client *cl = ch->client;
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u32 v;
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clk_enable(ch->clk);
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v = cl->flags & EP93XX_DMA_M2P_PORT_MASK;
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writel(v, ch->base + M2P_PPALLOC);
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v = cl->flags & EP93XX_DMA_M2P_ERROR_MASK;
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v |= M2P_CONTROL_ENABLE | M2P_CONTROL_ERROR_IRQ_EN;
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m2p_set_control(ch, v);
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}
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static void channel_disable(struct m2p_channel *ch)
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{
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u32 v;
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v = readl(ch->base + M2P_CONTROL);
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v &= ~(M2P_CONTROL_STALL_IRQ_EN | M2P_CONTROL_NFB_IRQ_EN);
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m2p_set_control(ch, v);
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while (m2p_channel_state(ch) == STATE_ON)
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cpu_relax();
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m2p_set_control(ch, 0x0);
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while (m2p_channel_state(ch) == STATE_STALL)
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cpu_relax();
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clk_disable(ch->clk);
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}
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int ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *cl)
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{
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struct m2p_channel *ch;
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int err;
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ch = find_free_channel(cl);
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if (IS_ERR(ch))
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return PTR_ERR(ch);
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err = request_irq(ch->irq, m2p_irq, 0, cl->name ? : "dma-m2p", ch);
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if (err)
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return err;
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ch->client = cl;
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ch->next_slot = 0;
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ch->buffer_xfer = NULL;
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ch->buffer_next = NULL;
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INIT_LIST_HEAD(&ch->buffers_pending);
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cl->channel = ch;
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channel_enable(ch);
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return 0;
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}
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EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_client_register);
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void ep93xx_dma_m2p_client_unregister(struct ep93xx_dma_m2p_client *cl)
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{
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struct m2p_channel *ch = cl->channel;
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channel_disable(ch);
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free_irq(ch->irq, ch);
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ch->client = NULL;
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}
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EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_client_unregister);
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void ep93xx_dma_m2p_submit(struct ep93xx_dma_m2p_client *cl,
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struct ep93xx_dma_buffer *buf)
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{
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struct m2p_channel *ch = cl->channel;
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unsigned long flags;
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u32 v;
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spin_lock_irqsave(&ch->lock, flags);
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v = readl(ch->base + M2P_CONTROL);
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if (ch->buffer_xfer == NULL) {
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ch->buffer_xfer = buf;
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feed_buf(ch, buf);
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cl->buffer_started(cl->cookie, buf);
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v |= M2P_CONTROL_STALL_IRQ_EN;
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m2p_set_control(ch, v);
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} else if (ch->buffer_next == NULL) {
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ch->buffer_next = buf;
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feed_buf(ch, buf);
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v |= M2P_CONTROL_NFB_IRQ_EN;
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m2p_set_control(ch, v);
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} else {
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list_add_tail(&buf->list, &ch->buffers_pending);
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}
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spin_unlock_irqrestore(&ch->lock, flags);
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}
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EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_submit);
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void ep93xx_dma_m2p_submit_recursive(struct ep93xx_dma_m2p_client *cl,
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struct ep93xx_dma_buffer *buf)
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{
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struct m2p_channel *ch = cl->channel;
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list_add_tail(&buf->list, &ch->buffers_pending);
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}
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EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_submit_recursive);
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void ep93xx_dma_m2p_flush(struct ep93xx_dma_m2p_client *cl)
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{
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struct m2p_channel *ch = cl->channel;
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channel_disable(ch);
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ch->next_slot = 0;
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ch->buffer_xfer = NULL;
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ch->buffer_next = NULL;
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INIT_LIST_HEAD(&ch->buffers_pending);
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channel_enable(ch);
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}
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EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_flush);
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static int init_channel(struct m2p_channel *ch)
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{
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ch->clk = clk_get(NULL, ch->name);
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if (IS_ERR(ch->clk))
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return PTR_ERR(ch->clk);
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spin_lock_init(&ch->lock);
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ch->client = NULL;
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return 0;
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}
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static int __init ep93xx_dma_m2p_init(void)
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{
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int i;
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int ret;
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for (i = 0; m2p_rx[i].base; i++) {
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ret = init_channel(m2p_rx + i);
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if (ret)
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return ret;
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}
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for (i = 0; m2p_tx[i].base; i++) {
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ret = init_channel(m2p_tx + i);
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if (ret)
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return ret;
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}
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pr_info("M2P DMA subsystem initialized\n");
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return 0;
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}
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arch_initcall(ep93xx_dma_m2p_init);
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52
arch/arm/mach-ep93xx/include/mach/dma.h
Normal file
52
arch/arm/mach-ep93xx/include/mach/dma.h
Normal file
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@ -0,0 +1,52 @@
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#ifndef __ASM_ARCH_DMA_H
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#define __ASM_ARCH_DMA_H
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#include <linux/list.h>
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#include <linux/types.h>
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struct ep93xx_dma_buffer {
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struct list_head list;
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u32 bus_addr;
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u16 size;
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};
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struct ep93xx_dma_m2p_client {
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char *name;
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u8 flags;
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void *cookie;
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void (*buffer_started)(void *cookie,
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struct ep93xx_dma_buffer *buf);
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void (*buffer_finished)(void *cookie,
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struct ep93xx_dma_buffer *buf,
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int bytes, int error);
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/* Internal to the DMA code. */
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void *channel;
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};
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#define EP93XX_DMA_M2P_PORT_I2S1 0x00
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#define EP93XX_DMA_M2P_PORT_I2S2 0x01
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#define EP93XX_DMA_M2P_PORT_AAC1 0x02
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#define EP93XX_DMA_M2P_PORT_AAC2 0x03
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#define EP93XX_DMA_M2P_PORT_AAC3 0x04
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#define EP93XX_DMA_M2P_PORT_I2S3 0x05
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#define EP93XX_DMA_M2P_PORT_UART1 0x06
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#define EP93XX_DMA_M2P_PORT_UART2 0x07
|
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#define EP93XX_DMA_M2P_PORT_UART3 0x08
|
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#define EP93XX_DMA_M2P_PORT_IRDA 0x09
|
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#define EP93XX_DMA_M2P_PORT_MASK 0x0f
|
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#define EP93XX_DMA_M2P_TX 0x00
|
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#define EP93XX_DMA_M2P_RX 0x10
|
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#define EP93XX_DMA_M2P_ABORT_ON_ERROR 0x20
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#define EP93XX_DMA_M2P_IGNORE_ERROR 0x40
|
||||
#define EP93XX_DMA_M2P_ERROR_MASK 0x60
|
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|
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int ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *m2p);
|
||||
void ep93xx_dma_m2p_client_unregister(struct ep93xx_dma_m2p_client *m2p);
|
||||
void ep93xx_dma_m2p_submit(struct ep93xx_dma_m2p_client *m2p,
|
||||
struct ep93xx_dma_buffer *buf);
|
||||
void ep93xx_dma_m2p_submit_recursive(struct ep93xx_dma_m2p_client *m2p,
|
||||
struct ep93xx_dma_buffer *buf);
|
||||
void ep93xx_dma_m2p_flush(struct ep93xx_dma_m2p_client *m2p);
|
||||
|
||||
#endif /* __ASM_ARCH_DMA_H */
|
||||
|
|
@ -58,7 +58,8 @@
|
|||
|
||||
|
||||
/* AHB peripherals */
|
||||
#define EP93XX_DMA_BASE (EP93XX_AHB_VIRT_BASE + 0x00000000)
|
||||
#define EP93XX_DMA_BASE ((void __iomem *) \
|
||||
(EP93XX_AHB_VIRT_BASE + 0x00000000))
|
||||
|
||||
#define EP93XX_ETHERNET_BASE (EP93XX_AHB_VIRT_BASE + 0x00010000)
|
||||
#define EP93XX_ETHERNET_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00010000)
|
||||
|
|
|
|||
Loading…
Reference in a new issue