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net: dsa: qca8k: check return value of read functions correctly
Current return type of qca8k_mii_read32() and qca8k_read() are unsigned, it can't be negative, so the return value check is unuseful. For check the return value correctly, change return type of the read functions and add a output parameter to store the read value. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Yang Yingliang
Jakub Kicinski
parent
320daffdf2
commit
7c9896e378
1 changed files with 60 additions and 70 deletions
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@ -89,26 +89,26 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
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*page = regaddr & 0x3ff;
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}
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static u32
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qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum)
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static int
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qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
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{
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u32 val;
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int ret;
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ret = bus->read(bus, phy_id, regnum);
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if (ret >= 0) {
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val = ret;
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*val = ret;
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ret = bus->read(bus, phy_id, regnum + 1);
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val |= ret << 16;
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*val |= ret << 16;
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}
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if (ret < 0) {
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dev_err_ratelimited(&bus->dev,
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"failed to read qca8k 32bit register\n");
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*val = 0;
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return ret;
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}
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return val;
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return 0;
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}
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static void
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@ -148,26 +148,26 @@ qca8k_set_page(struct mii_bus *bus, u16 page)
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return 0;
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}
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static u32
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qca8k_read(struct qca8k_priv *priv, u32 reg)
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static int
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qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
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{
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struct mii_bus *bus = priv->bus;
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u16 r1, r2, page;
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u32 val;
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int ret;
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qca8k_split_addr(reg, &r1, &r2, &page);
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mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
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val = qca8k_set_page(bus, page);
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if (val < 0)
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ret = qca8k_set_page(bus, page);
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if (ret < 0)
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goto exit;
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val = qca8k_mii_read32(bus, 0x10 | r2, r1);
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ret = qca8k_mii_read32(bus, 0x10 | r2, r1, val);
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exit:
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mutex_unlock(&bus->mdio_lock);
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return val;
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return ret;
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}
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static int
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@ -208,11 +208,9 @@ qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
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if (ret < 0)
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goto exit;
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val = qca8k_mii_read32(bus, 0x10 | r2, r1);
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if (val < 0) {
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ret = val;
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ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
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if (ret < 0)
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goto exit;
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}
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val &= ~mask;
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val |= write_val;
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@ -240,15 +238,8 @@ static int
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qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
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{
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struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
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int ret;
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ret = qca8k_read(priv, reg);
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if (ret < 0)
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return ret;
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*val = ret;
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return 0;
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return qca8k_read(priv, reg, val);
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}
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static int
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@ -296,18 +287,18 @@ static struct regmap_config qca8k_regmap_config = {
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static int
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qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
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{
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int ret, ret1;
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u32 val;
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int ret;
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ret = read_poll_timeout(qca8k_read, val, !(val & mask),
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ret = read_poll_timeout(qca8k_read, ret1, !(val & mask),
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0, QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
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priv, reg);
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priv, reg, &val);
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/* Check if qca8k_read has failed for a different reason
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* before returning -ETIMEDOUT
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*/
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if (ret < 0 && val < 0)
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return val;
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if (ret < 0 && ret1 < 0)
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return ret1;
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return ret;
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}
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@ -316,13 +307,13 @@ static int
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qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
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{
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u32 reg[4], val;
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int i;
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int i, ret;
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/* load the ARL table into an array */
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for (i = 0; i < 4; i++) {
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val = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4));
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if (val < 0)
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return val;
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ret = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4), &val);
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if (ret < 0)
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return ret;
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reg[i] = val;
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}
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@ -396,9 +387,9 @@ qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
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/* Check for table full violation when adding an entry */
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if (cmd == QCA8K_FDB_LOAD) {
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reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC);
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if (reg < 0)
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return reg;
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ret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, ®);
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if (ret < 0)
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return ret;
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if (reg & QCA8K_ATU_FUNC_FULL)
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return -1;
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}
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@ -477,9 +468,9 @@ qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)
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/* Check for table full violation when adding an entry */
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if (cmd == QCA8K_VLAN_LOAD) {
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reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC1);
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if (reg < 0)
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return reg;
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ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, ®);
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if (ret < 0)
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return ret;
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if (reg & QCA8K_VTU_FUNC1_FULL)
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return -ENOMEM;
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}
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@ -505,11 +496,9 @@ qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged)
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if (ret < 0)
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goto out;
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reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0);
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if (reg < 0) {
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ret = reg;
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ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®);
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if (ret < 0)
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goto out;
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}
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reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
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reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));
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if (untagged)
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@ -542,11 +531,9 @@ qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid)
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if (ret < 0)
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goto out;
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reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0);
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if (reg < 0) {
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ret = reg;
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ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®);
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if (ret < 0)
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goto out;
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}
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reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));
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reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<
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QCA8K_VTU_FUNC0_EG_MODE_S(port);
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@ -638,19 +625,19 @@ qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)
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{
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u16 r1, r2, page;
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u32 val;
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int ret;
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int ret, ret1;
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qca8k_split_addr(reg, &r1, &r2, &page);
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ret = read_poll_timeout(qca8k_mii_read32, val, !(val & mask), 0,
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ret = read_poll_timeout(qca8k_mii_read32, ret1, !(val & mask), 0,
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QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
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bus, 0x10 | r2, r1);
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bus, 0x10 | r2, r1, &val);
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/* Check if qca8k_read has failed for a different reason
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* before returnting -ETIMEDOUT
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*/
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if (ret < 0 && val < 0)
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return val;
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if (ret < 0 && ret1 < 0)
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return ret1;
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return ret;
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}
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@ -725,7 +712,7 @@ qca8k_mdio_read(struct mii_bus *salve_bus, int phy, int regnum)
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if (ret)
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goto exit;
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val = qca8k_mii_read32(bus, 0x10 | r2, r1);
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ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
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exit:
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/* even if the busy_wait timeouts try to clear the MASTER_EN */
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@ -733,10 +720,10 @@ qca8k_mdio_read(struct mii_bus *salve_bus, int phy, int regnum)
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mutex_unlock(&bus->mdio_lock);
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if (val >= 0)
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val &= QCA8K_MDIO_MASTER_DATA_MASK;
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if (ret >= 0)
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ret = val & QCA8K_MDIO_MASTER_DATA_MASK;
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return val;
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return ret;
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}
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static int
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@ -1211,7 +1198,7 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
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qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
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/* Enable/disable SerDes auto-negotiation as necessary */
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val = qca8k_read(priv, QCA8K_REG_PWS);
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qca8k_read(priv, QCA8K_REG_PWS, &val);
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if (phylink_autoneg_inband(mode))
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val &= ~QCA8K_PWS_SERDES_AEN_DIS;
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else
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@ -1219,7 +1206,7 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
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qca8k_write(priv, QCA8K_REG_PWS, val);
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/* Configure the SGMII parameters */
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val = qca8k_read(priv, QCA8K_REG_SGMII_CTRL);
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qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
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val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
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QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;
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@ -1314,10 +1301,11 @@ qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port,
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{
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struct qca8k_priv *priv = ds->priv;
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u32 reg;
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int ret;
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reg = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port));
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if (reg < 0)
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return reg;
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ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), ®);
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if (ret < 0)
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return ret;
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state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
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state->an_complete = state->link;
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@ -1419,19 +1407,20 @@ qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
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struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
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const struct qca8k_mib_desc *mib;
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u32 reg, i, val;
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u64 hi;
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u64 hi = 0;
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int ret;
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for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
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mib = &ar8327_mib[i];
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reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
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val = qca8k_read(priv, reg);
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if (val < 0)
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ret = qca8k_read(priv, reg, &val);
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if (ret < 0)
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continue;
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if (mib->size == 2) {
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hi = qca8k_read(priv, reg + 4);
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if (hi < 0)
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ret = qca8k_read(priv, reg + 4, (u32 *)&hi);
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if (ret < 0)
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continue;
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}
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@ -1459,7 +1448,7 @@ qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
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int ret;
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mutex_lock(&priv->reg_mutex);
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reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);
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ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, ®);
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if (reg < 0) {
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ret = reg;
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goto exit;
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@ -1793,14 +1782,15 @@ static int qca8k_read_switch_id(struct qca8k_priv *priv)
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const struct qca8k_match_data *data;
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u32 val;
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u8 id;
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int ret;
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/* get the switches ID from the compatible */
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data = of_device_get_match_data(priv->dev);
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if (!data)
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return -ENODEV;
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val = qca8k_read(priv, QCA8K_REG_MASK_CTRL);
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if (val < 0)
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ret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val);
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if (ret < 0)
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return -ENODEV;
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id = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK);
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