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ice: Introduce ETH56G PHY model for E825C products

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E825C products feature a new PHY model - ETH56G.

Introduces all necessary PHY definitions, functions etc. for ETH56G PHY,
analogous to E82X and E810 ones with addition of a few HW-specific
functionalities for ETH56G like one-step timestamping.

It ensures correct PTP initialization and operation for E825C products.

Co-developed-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Co-developed-by: Michal Michalik <michal.michalik@intel.com>
Signed-off-by: Michal Michalik <michal.michalik@intel.com>
Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Co-developed-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com>
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Link: https://lore.kernel.org/r/20240528-next-2024-05-28-ptp-refactors-v1-7-c082739bb6f6@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Sergey Temerkhanov 2024-05-28 16:03:57 -07:00 committed by Jakub Kicinski
parent 1f374d57c3
commit 7cab44f1c3
9 changed files with 2613 additions and 154 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

10
drivers/net/ethernet/intel/ice/ice_common.c
View file

@ -3067,11 +3067,13 @@ bool ice_is_100m_speed_supported(struct ice_hw *hw)
* Note: In the structure of [phy_type_low, phy_type_high], there should
* be one bit set, as this function will convert one PHY type to its
* speed.
* If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
* If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
*
* Return:
* * PHY speed for recognized PHY type
* * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
* * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
*/
static u16
ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
{
u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;

1
drivers/net/ethernet/intel/ice/ice_common.h
View file

@ -262,6 +262,7 @@ int
ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
bool *value, struct ice_sq_cd *cd);
bool ice_is_100m_speed_supported(struct ice_hw *hw);
u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high);
int
ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
struct ice_sq_cd *cd);

73
drivers/net/ethernet/intel/ice/ice_ptp.c
View file

@ -1011,6 +1011,28 @@ ice_ptp_release_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)
tx->len = 0;
}
/**
* ice_ptp_init_tx_eth56g - Initialize tracking for Tx timestamps
* @pf: Board private structure
* @tx: the Tx tracking structure to initialize
* @port: the port this structure tracks
*
* Initialize the Tx timestamp tracker for this port. ETH56G PHYs
* have independent memory blocks for all ports.
*
* Return: 0 for success, -ENOMEM when failed to allocate Tx tracker
*/
static int ice_ptp_init_tx_eth56g(struct ice_pf *pf, struct ice_ptp_tx *tx,
u8 port)
{
tx->block = port;
tx->offset = 0;
tx->len = INDEX_PER_PORT_ETH56G;
tx->has_ready_bitmap = 1;
return ice_ptp_alloc_tx_tracker(tx);
}
/**
* ice_ptp_init_tx_e82x - Initialize tracking for Tx timestamps
* @pf: Board private structure
@ -1341,10 +1363,19 @@ ice_ptp_port_phy_stop(struct ice_ptp_port *ptp_port)
mutex_lock(&ptp_port->ps_lock);
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G:
err = ice_stop_phy_timer_eth56g(hw, port, true);
break;
case ICE_PHY_E82X:
kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
err = ice_stop_phy_timer_e82x(hw, port, true);
if (err)
break;
default:
err = -ENODEV;
}
if (err && err != -EBUSY)
dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d down, err %d\n",
port, err);
@ -1378,9 +1409,17 @@ ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port)
mutex_lock(&ptp_port->ps_lock);
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G:
err = ice_start_phy_timer_eth56g(hw, port);
break;
case ICE_PHY_E82X:
/* Start the PHY timer in Vernier mode */
kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
/* temporarily disable Tx timestamps while calibrating PHY offset */
/* temporarily disable Tx timestamps while calibrating
* PHY offset
*/
spin_lock_irqsave(&ptp_port->tx.lock, flags);
ptp_port->tx.calibrating = true;
spin_unlock_irqrestore(&ptp_port->tx.lock, flags);
@ -1389,16 +1428,20 @@ ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port)
/* Start the PHY timer in Vernier mode */
err = ice_start_phy_timer_e82x(hw, port);
if (err)
goto out_unlock;
break;
/* Enable Tx timestamps right away */
spin_lock_irqsave(&ptp_port->tx.lock, flags);
ptp_port->tx.calibrating = false;
spin_unlock_irqrestore(&ptp_port->tx.lock, flags);
kthread_queue_delayed_work(pf->ptp.kworker, &ptp_port->ov_work, 0);
kthread_queue_delayed_work(pf->ptp.kworker, &ptp_port->ov_work,
0);
break;
default:
err = -ENODEV;
}
out_unlock:
if (err)
dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d up, err %d\n",
port, err);
@ -1436,6 +1479,7 @@ void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)
case ICE_PHY_E810:
/* Do not reconfigure E810 PHY */
return;
case ICE_PHY_ETH56G:
case ICE_PHY_E82X:
ice_ptp_port_phy_restart(ptp_port);
return;
@ -1465,6 +1509,22 @@ static int ice_ptp_cfg_phy_interrupt(struct ice_pf *pf, bool ena, u32 threshold)
ice_ptp_reset_ts_memory(hw);
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G: {
int port;
for (port = 0; port < hw->ptp.num_lports; port++) {
int err;
err = ice_phy_cfg_intr_eth56g(hw, port, ena, threshold);
if (err) {
dev_err(dev, "Failed to configure PHY interrupt for port %d, err %d\n",
port, err);
return err;
}
}
return 0;
}
case ICE_PHY_E82X: {
int quad;
@ -3075,6 +3135,9 @@ static int ice_ptp_init_port(struct ice_pf *pf, struct ice_ptp_port *ptp_port)
mutex_init(&ptp_port->ps_lock);
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G:
return ice_ptp_init_tx_eth56g(pf, &ptp_port->tx,
ptp_port->port_num);
case ICE_PHY_E810:
return ice_ptp_init_tx_e810(pf, &ptp_port->tx);
case ICE_PHY_E82X:

1
drivers/net/ethernet/intel/ice/ice_ptp.h
View file

@ -153,6 +153,7 @@ struct ice_ptp_tx {
#define INDEX_PER_QUAD 64
#define INDEX_PER_PORT_E82X 16
#define INDEX_PER_PORT_E810 64
#define INDEX_PER_PORT_ETH56G 64
/**
* struct ice_ptp_port - data used to initialize an external port for PTP

315
drivers/net/ethernet/intel/ice/ice_ptp_consts.h
View file

@ -9,6 +9,321 @@
*/
/* Constants defined for the PTP 1588 clock hardware. */
const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES] = {
/* ETH56G_PHY_REG_PTP */
{
/* base_addr */
{
0x092000,
0x126000,
0x1BA000,
0x24E000,
0x2E2000,
},
/* step */
0x98,
},
/* ETH56G_PHY_MEM_PTP */
{
/* base_addr */
{
0x093000,
0x127000,
0x1BB000,
0x24F000,
0x2E3000,
},
/* step */
0x200,
},
/* ETH56G_PHY_REG_XPCS */
{
/* base_addr */
{
0x000000,
0x009400,
0x128000,
0x1BC000,
0x250000,
},
/* step */
0x21000,
},
/* ETH56G_PHY_REG_MAC */
{
/* base_addr */
{
0x085000,
0x119000,
0x1AD000,
0x241000,
0x2D5000,
},
/* step */
0x1000,
},
/* ETH56G_PHY_REG_GPCS */
{
/* base_addr */
{
0x084000,
0x118000,
0x1AC000,
0x240000,
0x2D4000,
},
/* step */
0x400,
},
};
const
struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD] = {
[ICE_ETH56G_LNK_SPD_1G] = {
.tx_mode = { .def = 6, },
.rx_mode = { .def = 6, },
.blks_per_clk = 1,
.blktime = 0x4000, /* 32 */
.tx_offset = {
.serdes = 0x6666, /* 51.2 */
.no_fec = 0xd066, /* 104.2 */
.sfd = 0x3000, /* 24 */
.onestep = 0x30000 /* 384 */
},
.rx_offset = {
.serdes = 0xffffc59a, /* -29.2 */
.no_fec = 0xffff0a80, /* -122.75 */
.sfd = 0x2c00, /* 22 */
.bs_ds = 0x19a /* 0.8 */
/* Dynamic bitslip 0 equals to 10 */
}
},
[ICE_ETH56G_LNK_SPD_2_5G] = {
.tx_mode = { .def = 6, },
.rx_mode = { .def = 6, },
.blks_per_clk = 1,
.blktime = 0x199a, /* 12.8 */
.tx_offset = {
.serdes = 0x28f6, /* 20.48 */
.no_fec = 0x53b8, /* 41.86 */
.sfd = 0x1333, /* 9.6 */
.onestep = 0x13333 /* 153.6 */
},
.rx_offset = {
.serdes = 0xffffe8a4, /* -11.68 */
.no_fec = 0xffff9a76, /* -50.77 */
.sfd = 0xf33, /* 7.6 */
.bs_ds = 0xa4 /* 0.32 */
}
},
[ICE_ETH56G_LNK_SPD_10G] = {
.tx_mode = { .def = 1, },
.rx_mode = { .def = 1, },
.blks_per_clk = 1,
.blktime = 0x666, /* 3.2 */
.tx_offset = {
.serdes = 0x234c, /* 17.6484848 */
.no_fec = 0x8e80, /* 71.25 */
.fc = 0xb4a4, /* 90.32 */
.sfd = 0x4a4, /* 2.32 */
.onestep = 0x4ccd /* 38.4 */
},
.rx_offset = {
.serdes = 0xffffeb27, /* -10.42424 */
.no_fec = 0xffffcccd, /* -25.6 */
.fc = 0xfffe0014, /* -255.96 */
.sfd = 0x4a4, /* 2.32 */
.bs_ds = 0x32 /* 0.0969697 */
}
},
[ICE_ETH56G_LNK_SPD_25G] = {
.tx_mode = {
.def = 1,
.rs = 4
},
.tx_mk_dly = 4,
.tx_cw_dly = {
.def = 1,
.onestep = 6
},
.rx_mode = {
.def = 1,
.rs = 4
},
.rx_mk_dly = {
.def = 1,
.rs = 1
},
.rx_cw_dly = {
.def = 1,
.rs = 1
},
.blks_per_clk = 1,
.blktime = 0x28f, /* 1.28 */
.mktime = 0x147b, /* 10.24, only if RS-FEC enabled */
.tx_offset = {
.serdes = 0xe1e, /* 7.0593939 */
.no_fec = 0x3857, /* 28.17 */
.fc = 0x48c3, /* 36.38 */
.rs = 0x8100, /* 64.5 */
.sfd = 0x1dc, /* 0.93 */
.onestep = 0x1eb8 /* 15.36 */
},
.rx_offset = {
.serdes = 0xfffff7a9, /* -4.1697 */
.no_fec = 0xffffe71a, /* -12.45 */
.fc = 0xfffe894d, /* -187.35 */
.rs = 0xfffff8cd, /* -3.6 */
.sfd = 0x1dc, /* 0.93 */
.bs_ds = 0x14 /* 0.0387879, RS-FEC 0 */
}
},
[ICE_ETH56G_LNK_SPD_40G] = {
.tx_mode = { .def = 3 },
.tx_mk_dly = 4,
.tx_cw_dly = {
.def = 1,
.onestep = 6
},
.rx_mode = { .def = 4 },
.rx_mk_dly = { .def = 1 },
.rx_cw_dly = { .def = 1 },
.blktime = 0x333, /* 1.6 */
.mktime = 0xccd, /* 6.4 */
.tx_offset = {
.serdes = 0x234c, /* 17.6484848 */
.no_fec = 0x5a8a, /* 45.27 */
.fc = 0x81b8, /* 64.86 */
.sfd = 0x4a4, /* 2.32 */
.onestep = 0x1333 /* 9.6 */
},
.rx_offset = {
.serdes = 0xffffeb27, /* -10.42424 */
.no_fec = 0xfffff594, /* -5.21 */
.fc = 0xfffe3080, /* -231.75 */
.sfd = 0x4a4, /* 2.32 */
.bs_ds = 0xccd /* 6.4 */
}
},
[ICE_ETH56G_LNK_SPD_50G] = {
.tx_mode = { .def = 5 },
.tx_mk_dly = 4,
.tx_cw_dly = {
.def = 1,
.onestep = 6
},
.rx_mode = { .def = 5 },
.rx_mk_dly = { .def = 1 },
.rx_cw_dly = { .def = 1 },
.blktime = 0x28f, /* 1.28 */
.mktime = 0xa3d, /* 5.12 */
.tx_offset = {
.serdes = 0x13ba, /* 9.86353 */
.rs = 0x5400, /* 42 */
.sfd = 0xe6, /* 0.45 */
.onestep = 0xf5c /* 7.68 */
},
.rx_offset = {
.serdes = 0xfffff7e8, /* -4.04706 */
.rs = 0xfffff994, /* -3.21 */
.sfd = 0xe6 /* 0.45 */
}
},
[ICE_ETH56G_LNK_SPD_50G2] = {
.tx_mode = {
.def = 3,
.rs = 2
},
.tx_mk_dly = 4,
.tx_cw_dly = {
.def = 1,
.onestep = 6
},
.rx_mode = {
.def = 4,
.rs = 1
},
.rx_mk_dly = { .def = 1 },
.rx_cw_dly = { .def = 1 },
.blktime = 0x28f, /* 1.28 */
.mktime = 0xa3d, /* 5.12 */
.tx_offset = {
.serdes = 0xe1e, /* 7.0593939 */
.no_fec = 0x3d33, /* 30.6 */
.rs = 0x5057, /* 40.17 */
.sfd = 0x1dc, /* 0.93 */
.onestep = 0xf5c /* 7.68 */
},
.rx_offset = {
.serdes = 0xfffff7a9, /* -4.1697 */
.no_fec = 0xfffff8cd, /* -3.6 */
.rs = 0xfffff21a, /* -6.95 */
.sfd = 0x1dc, /* 0.93 */
.bs_ds = 0xa3d /* 5.12, RS-FEC 0x633 (3.1) */
}
},
[ICE_ETH56G_LNK_SPD_100G] = {
.tx_mode = {
.def = 3,
.rs = 2
},
.tx_mk_dly = 10,
.tx_cw_dly = {
.def = 3,
.onestep = 6
},
.rx_mode = {
.def = 4,
.rs = 1
},
.rx_mk_dly = { .def = 5 },
.rx_cw_dly = { .def = 5 },
.blks_per_clk = 1,
.blktime = 0x148, /* 0.64 */
.mktime = 0x199a, /* 12.8 */
.tx_offset = {
.serdes = 0xe1e, /* 7.0593939 */
.no_fec = 0x67ec, /* 51.96 */
.rs = 0x44fb, /* 34.49 */
.sfd = 0x1dc, /* 0.93 */
.onestep = 0xf5c /* 7.68 */
},
.rx_offset = {
.serdes = 0xfffff7a9, /* -4.1697 */
.no_fec = 0xfffff5a9, /* -5.17 */
.rs = 0xfffff6e6, /* -4.55 */
.sfd = 0x1dc, /* 0.93 */
.bs_ds = 0x199a /* 12.8, RS-FEC 0x31b (1.552) */
}
},
[ICE_ETH56G_LNK_SPD_100G2] = {
.tx_mode = { .def = 5 },
.tx_mk_dly = 10,
.tx_cw_dly = {
.def = 3,
.onestep = 6
},
.rx_mode = { .def = 5 },
.rx_mk_dly = { .def = 5 },
.rx_cw_dly = { .def = 5 },
.blks_per_clk = 1,
.blktime = 0x148, /* 0.64 */
.mktime = 0x199a, /* 12.8 */
.tx_offset = {
.serdes = 0x13ba, /* 9.86353 */
.rs = 0x460a, /* 35.02 */
.sfd = 0xe6, /* 0.45 */
.onestep = 0xf5c /* 7.68 */
},
.rx_offset = {
.serdes = 0xfffff7e8, /* -4.04706 */
.rs = 0xfffff548, /* -5.36 */
.sfd = 0xe6, /* 0.45 */
.bs_ds = 0x303 /* 1.506 */
}
}
};
/* struct ice_time_ref_info_e82x
*
* E822 hardware can use different sources as the reference for the PTP

2069
drivers/net/ethernet/intel/ice/ice_ptp_hw.c
View file

File diff suppressed because it is too large Load diff

238
drivers/net/ethernet/intel/ice/ice_ptp_hw.h
View file

@ -41,6 +41,41 @@ enum ice_ptp_fec_mode {
ICE_PTP_FEC_MODE_RS_FEC
};
enum eth56g_res_type {
ETH56G_PHY_REG_PTP,
ETH56G_PHY_MEM_PTP,
ETH56G_PHY_REG_XPCS,
ETH56G_PHY_REG_MAC,
ETH56G_PHY_REG_GPCS,
NUM_ETH56G_PHY_RES
};
enum ice_eth56g_link_spd {
ICE_ETH56G_LNK_SPD_1G,
ICE_ETH56G_LNK_SPD_2_5G,
ICE_ETH56G_LNK_SPD_10G,
ICE_ETH56G_LNK_SPD_25G,
ICE_ETH56G_LNK_SPD_40G,
ICE_ETH56G_LNK_SPD_50G,
ICE_ETH56G_LNK_SPD_50G2,
ICE_ETH56G_LNK_SPD_100G,
ICE_ETH56G_LNK_SPD_100G2,
NUM_ICE_ETH56G_LNK_SPD /* Must be last */
};
/**
* struct ice_phy_reg_info_eth56g - ETH56G PHY register parameters
* @base: base address for each PHY block
* @step: step between PHY lanes
*
* Characteristic information for the various PHY register parameters in the
* ETH56G devices
*/
struct ice_phy_reg_info_eth56g {
u32 base[NUM_ETH56G_PHY_RES];
u32 step;
};
/**
* struct ice_time_ref_info_e82x
* @pll_freq: Frequency of PLL that drives timer ticks in Hz
@ -94,6 +129,73 @@ struct ice_vernier_info_e82x {
u32 rx_fixed_delay;
};
#define ICE_ETH56G_MAC_CFG_RX_OFFSET_INT GENMASK(19, 9)
#define ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC GENMASK(8, 0)
#define ICE_ETH56G_MAC_CFG_FRAC_W 9
/**
* struct ice_eth56g_mac_reg_cfg - MAC config values for specific PTP registers
* @tx_mode: Tx timestamp compensation mode
* @tx_mk_dly: Tx timestamp marker start strobe delay
* @tx_cw_dly: Tx timestamp codeword start strobe delay
* @rx_mode: Rx timestamp compensation mode
* @rx_mk_dly: Rx timestamp marker start strobe delay
* @rx_cw_dly: Rx timestamp codeword start strobe delay
* @blks_per_clk: number of blocks transferred per clock cycle
* @blktime: block time, fixed point
* @mktime: marker time, fixed point
* @tx_offset: total Tx offset, fixed point
* @rx_offset: total Rx offset, contains value for bitslip/deskew, fixed point
*
* All fixed point registers except Rx offset are 23 bit unsigned ints with
* a 9 bit fractional.
* Rx offset is 11 bit unsigned int with a 9 bit fractional.
*/
struct ice_eth56g_mac_reg_cfg {
struct {
u8 def;
u8 rs;
} tx_mode;
u8 tx_mk_dly;
struct {
u8 def;
u8 onestep;
} tx_cw_dly;
struct {
u8 def;
u8 rs;
} rx_mode;
struct {
u8 def;
u8 rs;
} rx_mk_dly;
struct {
u8 def;
u8 rs;
} rx_cw_dly;
u8 blks_per_clk;
u16 blktime;
u16 mktime;
struct {
u32 serdes;
u32 no_fec;
u32 fc;
u32 rs;
u32 sfd;
u32 onestep;
} tx_offset;
struct {
u32 serdes;
u32 no_fec;
u32 fc;
u32 rs;
u32 sfd;
u32 bs_ds;
} rx_offset;
};
extern
const struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD];
/**
* struct ice_cgu_pll_params_e82x
* @refclk_pre_div: Reference clock pre-divisor
@ -188,6 +290,9 @@ ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ];
#define E810C_QSFP_C827_0_HANDLE 2
#define E810C_QSFP_C827_1_HANDLE 3
/* Table of constants related to possible ETH56G PHY resources */
extern const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES];
/* Table of constants related to possible TIME_REF sources */
extern const struct ice_time_ref_info_e82x e822_time_ref[NUM_ICE_TIME_REF_FREQ];
@ -197,7 +302,9 @@ extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD];
/* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
* the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
*/
#define ICE_E810_PLL_FREQ 812500000
#define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
#define E810_OUT_PROP_DELAY_NS 1
/* Device agnostic functions */
u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
@ -215,6 +322,8 @@ void ice_ptp_reset_ts_memory(struct ice_hw *hw);
int ice_ptp_init_phc(struct ice_hw *hw);
void ice_ptp_init_hw(struct ice_hw *hw);
int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready);
int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
enum ice_ptp_tmr_cmd configured_cmd);
/* E822 family functions */
int ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);
@ -285,6 +394,21 @@ int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num);
int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
unsigned long *caps);
/* ETH56G family functions */
int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status);
int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset);
int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port);
int ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port);
int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port);
int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold);
int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port);
#define ICE_ETH56G_NOMINAL_INCVAL 0x140000000ULL
#define ICE_ETH56G_NOMINAL_PCS_REF_TUS 0x100000000ULL
#define ICE_ETH56G_NOMINAL_PCS_REF_INC 0x300000000ULL
#define ICE_ETH56G_NOMINAL_THRESH4 0x7777
#define ICE_ETH56G_NOMINAL_TX_THRESH 0x6
/**
* ice_get_base_incval - Get base clock increment value
* @hw: pointer to the HW struct
@ -294,6 +418,8 @@ int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
static inline u64 ice_get_base_incval(struct ice_hw *hw)
{
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G:
return ICE_ETH56G_NOMINAL_INCVAL;
case ICE_PHY_E810:
return ICE_PTP_NOMINAL_INCVAL_E810;
case ICE_PHY_E82X:
@ -330,6 +456,7 @@ static inline u64 ice_get_base_incval(struct ice_hw *hw)
#define TS_CMD_MASK_E810 0xFF
#define TS_CMD_MASK 0xF
#define SYNC_EXEC_CMD 0x3
#define TS_CMD_RX_TYPE ICE_M(0x18, 0x4)
/* Macros to derive port low and high addresses on both quads */
#define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
@ -564,4 +691,115 @@ static inline u64 ice_get_base_incval(struct ice_hw *hw)
/* E810T PCA9575 IO controller pin control */
#define ICE_E810T_P0_GNSS_PRSNT_N BIT(4)
/* ETH56G PHY register addresses */
/* Timestamp PHY incval registers */
#define PHY_REG_TIMETUS_L 0x8
#define PHY_REG_TIMETUS_U 0xC
/* Timestamp PCS registers */
#define PHY_PCS_REF_TUS_L 0x18
#define PHY_PCS_REF_TUS_U 0x1C
/* Timestamp PCS ref incval registers */
#define PHY_PCS_REF_INC_L 0x20
#define PHY_PCS_REF_INC_U 0x24
/* Timestamp init registers */
#define PHY_REG_RX_TIMER_INC_PRE_L 0x64
#define PHY_REG_RX_TIMER_INC_PRE_U 0x68
#define PHY_REG_TX_TIMER_INC_PRE_L 0x44
#define PHY_REG_TX_TIMER_INC_PRE_U 0x48
/* Timestamp match and adjust target registers */
#define PHY_REG_RX_TIMER_CNT_ADJ_L 0x6C
#define PHY_REG_RX_TIMER_CNT_ADJ_U 0x70
#define PHY_REG_TX_TIMER_CNT_ADJ_L 0x4C
#define PHY_REG_TX_TIMER_CNT_ADJ_U 0x50
/* Timestamp command registers */
#define PHY_REG_TX_TMR_CMD 0x40
#define PHY_REG_RX_TMR_CMD 0x60
/* Phy offset ready registers */
#define PHY_REG_TX_OFFSET_READY 0x54
#define PHY_REG_RX_OFFSET_READY 0x74
/* Phy total offset registers */
#define PHY_REG_TOTAL_TX_OFFSET_L 0x38
#define PHY_REG_TOTAL_TX_OFFSET_U 0x3C
#define PHY_REG_TOTAL_RX_OFFSET_L 0x58
#define PHY_REG_TOTAL_RX_OFFSET_U 0x5C
/* Timestamp capture registers */
#define PHY_REG_TX_CAPTURE_L 0x78
#define PHY_REG_TX_CAPTURE_U 0x7C
#define PHY_REG_RX_CAPTURE_L 0x8C
#define PHY_REG_RX_CAPTURE_U 0x90
/* Memory status registers */
#define PHY_REG_TX_MEMORY_STATUS_L 0x80
#define PHY_REG_TX_MEMORY_STATUS_U 0x84
/* Interrupt config register */
#define PHY_REG_TS_INT_CONFIG 0x88
/* XIF mode config register */
#define PHY_MAC_XIF_MODE 0x24
#define PHY_MAC_XIF_1STEP_ENA_M ICE_M(0x1, 5)
#define PHY_MAC_XIF_TS_BIN_MODE_M ICE_M(0x1, 11)
#define PHY_MAC_XIF_TS_SFD_ENA_M ICE_M(0x1, 20)
#define PHY_MAC_XIF_GMII_TS_SEL_M ICE_M(0x1, 21)
/* GPCS config register */
#define PHY_GPCS_CONFIG_REG0 0x268
#define PHY_GPCS_CONFIG_REG0_TX_THR_M ICE_M(0xF, 24)
#define PHY_GPCS_BITSLIP 0x5C
#define PHY_TS_INT_CONFIG_THRESHOLD_M ICE_M(0x3F, 0)
#define PHY_TS_INT_CONFIG_ENA_M BIT(6)
/* 1-step PTP config */
#define PHY_PTP_1STEP_CONFIG 0x270
#define PHY_PTP_1STEP_T1S_UP64_M ICE_M(0xF, 4)
#define PHY_PTP_1STEP_T1S_DELTA_M ICE_M(0xF, 8)
#define PHY_PTP_1STEP_PEER_DELAY(_port) (0x274 + 4 * (_port))
#define PHY_PTP_1STEP_PD_ADD_PD_M ICE_M(0x1, 0)
#define PHY_PTP_1STEP_PD_DELAY_M ICE_M(0x3fffffff, 1)
#define PHY_PTP_1STEP_PD_DLY_V_M ICE_M(0x1, 31)
/* Macros to derive offsets for TimeStampLow and TimeStampHigh */
#define PHY_TSTAMP_L(x) (((x) * 8) + 0)
#define PHY_TSTAMP_U(x) (((x) * 8) + 4)
#define PHY_REG_REVISION 0x85000
#define PHY_REG_DESKEW_0 0x94
#define PHY_REG_DESKEW_0_RLEVEL GENMASK(6, 0)
#define PHY_REG_DESKEW_0_RLEVEL_FRAC GENMASK(9, 7)
#define PHY_REG_DESKEW_0_RLEVEL_FRAC_W 3
#define PHY_REG_DESKEW_0_VALID GENMASK(10, 10)
#define PHY_REG_GPCS_BITSLIP 0x5C
#define PHY_REG_SD_BIT_SLIP(_port_offset) (0x29C + 4 * (_port_offset))
#define PHY_REVISION_ETH56G 0x10200
#define PHY_VENDOR_TXLANE_THRESH 0x2000C
#define PHY_MAC_TSU_CONFIG 0x40
#define PHY_MAC_TSU_CFG_RX_MODE_M ICE_M(0x7, 0)
#define PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M ICE_M(0x7, 4)
#define PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M ICE_M(0x7, 8)
#define PHY_MAC_TSU_CFG_TX_MODE_M ICE_M(0x7, 12)
#define PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M ICE_M(0x1F, 16)
#define PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M ICE_M(0x1F, 21)
#define PHY_MAC_TSU_CFG_BLKS_PER_CLK_M ICE_M(0x1, 28)
#define PHY_MAC_RX_MODULO 0x44
#define PHY_MAC_RX_OFFSET 0x48
#define PHY_MAC_RX_OFFSET_M ICE_M(0xFFFFFF, 0)
#define PHY_MAC_TX_MODULO 0x4C
#define PHY_MAC_BLOCKTIME 0x50
#define PHY_MAC_MARKERTIME 0x54
#define PHY_MAC_TX_OFFSET 0x58
#define PHY_PTP_INT_STATUS 0x7FD140
#endif /* _ICE_PTP_HW_H_ */

4
drivers/net/ethernet/intel/ice/ice_sbq_cmd.h
View file

@ -47,10 +47,12 @@ struct ice_sbq_evt_desc {
};
enum ice_sbq_msg_dev {
eth56g_phy_0 = 0x02,
rmn_0 = 0x02,
rmn_1 = 0x03,
rmn_2 = 0x04,
cgu = 0x06
cgu = 0x06,
eth56g_phy_1 = 0x0D,
};
enum ice_sbq_msg_opcode {

18
drivers/net/ethernet/intel/ice/ice_type.h
View file

@ -322,7 +322,9 @@ enum ice_time_ref_freq {
ICE_TIME_REF_FREQ_156_250 = 4,
ICE_TIME_REF_FREQ_245_760 = 5,
NUM_ICE_TIME_REF_FREQ
NUM_ICE_TIME_REF_FREQ,
ICE_TIME_REF_FREQ_INVALID = -1,
};
/* Clock source specification */
@ -821,15 +823,29 @@ struct ice_mbx_data {
#define ICE_PORTS_PER_QUAD 4
#define ICE_GET_QUAD_NUM(port) ((port) / ICE_PORTS_PER_QUAD)
struct ice_eth56g_params {
u8 num_phys;
u8 phy_addr[2];
bool onestep_ena;
bool sfd_ena;
u32 peer_delay;
};
union ice_phy_params {
struct ice_eth56g_params eth56g;
};
/* PHY model */
enum ice_phy_model {
ICE_PHY_UNSUP = -1,
ICE_PHY_E810 = 1,
ICE_PHY_E82X,
ICE_PHY_ETH56G,
};
struct ice_ptp_hw {
enum ice_phy_model phy_model;
union ice_phy_params phy;
u8 num_lports;
u8 ports_per_phy;
};