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drm/amdgpu: Add more checks to PSP mailbox

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Instead of checking the response flag, use status mask also to check
against any unexpected failures like a device drop. Also, log error if
waiting on a psp response fails/times out.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar 2025-06-02 12:55:14 +05:30 committed by Alex Deucher
parent 5562b66992
commit 8345a71fc5
9 changed files with 107 additions and 61 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

4
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
View file

@ -597,6 +597,10 @@ int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
udelay(1); udelay(1);
} }
dev_err(adev->dev,
"psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x",
reg_index, mask, val, reg_val);
return -ETIME; return -ETIME;
} }

11
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
View file

@ -51,6 +51,17 @@
#define C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_HI 0x10 #define C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_HI 0x10
#define C2PMSG_CMD_SPI_GET_FLASH_IMAGE 0x11 #define C2PMSG_CMD_SPI_GET_FLASH_IMAGE 0x11
/* Command register bit 31 set to indicate readiness */
#define MBOX_TOS_READY_FLAG (GFX_FLAG_RESPONSE)
#define MBOX_TOS_READY_MASK (GFX_CMD_RESPONSE_MASK | GFX_CMD_STATUS_MASK)
/* Values to check for a successful GFX_CMD response wait. Check against
* both status bits and response state - helps to detect a command failure
* or other unexpected cases like a device drop reading all 0xFFs
*/
#define MBOX_TOS_RESP_FLAG (GFX_FLAG_RESPONSE)
#define MBOX_TOS_RESP_MASK (GFX_CMD_RESPONSE_MASK | GFX_CMD_STATUS_MASK)
extern const struct attribute_group amdgpu_flash_attr_group; extern const struct attribute_group amdgpu_flash_attr_group;
enum psp_shared_mem_size { enum psp_shared_mem_size {

4
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
View file

@ -94,7 +94,7 @@ static int psp_v10_0_ring_create(struct psp_context *psp,
/* Wait for response flag (bit 31) in C2PMSG_64 */ /* Wait for response flag (bit 31) in C2PMSG_64 */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0x80000000, 0x8000FFFF, false); MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
return ret; return ret;
} }
@ -115,7 +115,7 @@ static int psp_v10_0_ring_stop(struct psp_context *psp,
/* Wait for response flag (bit 31) in C2PMSG_64 */ /* Wait for response flag (bit 31) in C2PMSG_64 */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0x80000000, 0x80000000, false); MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
return ret; return ret;
} }

31
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
View file

@ -277,11 +277,13 @@ static int psp_v11_0_ring_stop(struct psp_context *psp,
/* Wait for response flag (bit 31) */ /* Wait for response flag (bit 31) */
if (amdgpu_sriov_vf(adev)) if (amdgpu_sriov_vf(adev))
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), ret = psp_wait_for(
0x80000000, 0x80000000, false); psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
else else
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), ret = psp_wait_for(
0x80000000, 0x80000000, false); psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
return ret; return ret;
} }
@ -317,13 +319,15 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
mdelay(20); mdelay(20);
/* Wait for response flag (bit 31) in C2PMSG_101 */ /* Wait for response flag (bit 31) in C2PMSG_101 */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), ret = psp_wait_for(
0x80000000, 0x8000FFFF, false); psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
} else { } else {
/* Wait for sOS ready for ring creation */ /* Wait for sOS ready for ring creation */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), ret = psp_wait_for(
0x80000000, 0x80000000, false); psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
if (ret) { if (ret) {
DRM_ERROR("Failed to wait for sOS ready for ring creation\n"); DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
return ret; return ret;
@ -347,8 +351,9 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
mdelay(20); mdelay(20);
/* Wait for response flag (bit 31) in C2PMSG_64 */ /* Wait for response flag (bit 31) in C2PMSG_64 */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), ret = psp_wait_for(
0x80000000, 0x8000FFFF, false); psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
} }
return ret; return ret;
@ -381,7 +386,8 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp)
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG,
MBOX_TOS_READY_MASK, false);
if (ret) { if (ret) {
DRM_INFO("psp is not working correctly before mode1 reset!\n"); DRM_INFO("psp is not working correctly before mode1 reset!\n");
@ -395,7 +401,8 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp)
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK,
false);
if (ret) { if (ret) {
DRM_INFO("psp mode 1 reset failed!\n"); DRM_INFO("psp mode 1 reset failed!\n");

25
drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c
View file

@ -41,8 +41,9 @@ static int psp_v11_0_8_ring_stop(struct psp_context *psp,
/* there might be handshake issue with hardware which needs delay */ /* there might be handshake issue with hardware which needs delay */
mdelay(20); mdelay(20);
/* Wait for response flag (bit 31) */ /* Wait for response flag (bit 31) */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), ret = psp_wait_for(
0x80000000, 0x80000000, false); psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
} else { } else {
/* Write the ring destroy command*/ /* Write the ring destroy command*/
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
@ -50,8 +51,9 @@ static int psp_v11_0_8_ring_stop(struct psp_context *psp,
/* there might be handshake issue with hardware which needs delay */ /* there might be handshake issue with hardware which needs delay */
mdelay(20); mdelay(20);
/* Wait for response flag (bit 31) */ /* Wait for response flag (bit 31) */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), ret = psp_wait_for(
0x80000000, 0x80000000, false); psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
} }
return ret; return ret;
@ -87,13 +89,15 @@ static int psp_v11_0_8_ring_create(struct psp_context *psp,
mdelay(20); mdelay(20);
/* Wait for response flag (bit 31) in C2PMSG_101 */ /* Wait for response flag (bit 31) in C2PMSG_101 */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), ret = psp_wait_for(
0x80000000, 0x8000FFFF, false); psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
} else { } else {
/* Wait for sOS ready for ring creation */ /* Wait for sOS ready for ring creation */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), ret = psp_wait_for(
0x80000000, 0x80000000, false); psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
if (ret) { if (ret) {
DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
return ret; return ret;
@ -117,8 +121,9 @@ static int psp_v11_0_8_ring_create(struct psp_context *psp,
mdelay(20); mdelay(20);
/* Wait for response flag (bit 31) in C2PMSG_64 */ /* Wait for response flag (bit 31) in C2PMSG_64 */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), ret = psp_wait_for(
0x80000000, 0x8000FFFF, false); psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
} }
return ret; return ret;

18
drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
View file

@ -163,7 +163,7 @@ static int psp_v12_0_ring_create(struct psp_context *psp,
/* Wait for response flag (bit 31) in C2PMSG_64 */ /* Wait for response flag (bit 31) in C2PMSG_64 */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0x80000000, 0x8000FFFF, false); MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
return ret; return ret;
} }
@ -184,11 +184,13 @@ static int psp_v12_0_ring_stop(struct psp_context *psp,
/* Wait for response flag (bit 31) */ /* Wait for response flag (bit 31) */
if (amdgpu_sriov_vf(adev)) if (amdgpu_sriov_vf(adev))
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), ret = psp_wait_for(
0x80000000, 0x80000000, false); psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
else else
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), ret = psp_wait_for(
0x80000000, 0x80000000, false); psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
return ret; return ret;
} }
@ -219,7 +221,8 @@ static int psp_v12_0_mode1_reset(struct psp_context *psp)
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG,
MBOX_TOS_READY_MASK, false);
if (ret) { if (ret) {
DRM_INFO("psp is not working correctly before mode1 reset!\n"); DRM_INFO("psp is not working correctly before mode1 reset!\n");
@ -233,7 +236,8 @@ static int psp_v12_0_mode1_reset(struct psp_context *psp)
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK,
false);
if (ret) { if (ret) {
DRM_INFO("psp mode 1 reset failed!\n"); DRM_INFO("psp mode 1 reset failed!\n");

25
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
View file

@ -384,8 +384,9 @@ static int psp_v13_0_ring_stop(struct psp_context *psp,
/* there might be handshake issue with hardware which needs delay */ /* there might be handshake issue with hardware which needs delay */
mdelay(20); mdelay(20);
/* Wait for response flag (bit 31) */ /* Wait for response flag (bit 31) */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), ret = psp_wait_for(
0x80000000, 0x80000000, false); psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
} else { } else {
/* Write the ring destroy command*/ /* Write the ring destroy command*/
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
@ -393,8 +394,9 @@ static int psp_v13_0_ring_stop(struct psp_context *psp,
/* there might be handshake issue with hardware which needs delay */ /* there might be handshake issue with hardware which needs delay */
mdelay(20); mdelay(20);
/* Wait for response flag (bit 31) */ /* Wait for response flag (bit 31) */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), ret = psp_wait_for(
0x80000000, 0x80000000, false); psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
} }
return ret; return ret;
@ -430,13 +432,15 @@ static int psp_v13_0_ring_create(struct psp_context *psp,
mdelay(20); mdelay(20);
/* Wait for response flag (bit 31) in C2PMSG_101 */ /* Wait for response flag (bit 31) in C2PMSG_101 */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), ret = psp_wait_for(
0x80000000, 0x8000FFFF, false); psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
} else { } else {
/* Wait for sOS ready for ring creation */ /* Wait for sOS ready for ring creation */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), ret = psp_wait_for(
0x80000000, 0x80000000, false); psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
if (ret) { if (ret) {
DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
return ret; return ret;
@ -460,8 +464,9 @@ static int psp_v13_0_ring_create(struct psp_context *psp,
mdelay(20); mdelay(20);
/* Wait for response flag (bit 31) in C2PMSG_64 */ /* Wait for response flag (bit 31) in C2PMSG_64 */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), ret = psp_wait_for(
0x80000000, 0x8000FFFF, false); psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
} }
return ret; return ret;

25
drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c
View file

@ -204,8 +204,9 @@ static int psp_v13_0_4_ring_stop(struct psp_context *psp,
/* there might be handshake issue with hardware which needs delay */ /* there might be handshake issue with hardware which needs delay */
mdelay(20); mdelay(20);
/* Wait for response flag (bit 31) */ /* Wait for response flag (bit 31) */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), ret = psp_wait_for(
0x80000000, 0x80000000, false); psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
} else { } else {
/* Write the ring destroy command*/ /* Write the ring destroy command*/
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
@ -213,8 +214,9 @@ static int psp_v13_0_4_ring_stop(struct psp_context *psp,
/* there might be handshake issue with hardware which needs delay */ /* there might be handshake issue with hardware which needs delay */
mdelay(20); mdelay(20);
/* Wait for response flag (bit 31) */ /* Wait for response flag (bit 31) */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), ret = psp_wait_for(
0x80000000, 0x80000000, false); psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
} }
return ret; return ret;
@ -250,13 +252,15 @@ static int psp_v13_0_4_ring_create(struct psp_context *psp,
mdelay(20); mdelay(20);
/* Wait for response flag (bit 31) in C2PMSG_101 */ /* Wait for response flag (bit 31) in C2PMSG_101 */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), ret = psp_wait_for(
0x80000000, 0x8000FFFF, false); psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
} else { } else {
/* Wait for sOS ready for ring creation */ /* Wait for sOS ready for ring creation */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), ret = psp_wait_for(
0x80000000, 0x80000000, false); psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
if (ret) { if (ret) {
DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
return ret; return ret;
@ -280,8 +284,9 @@ static int psp_v13_0_4_ring_create(struct psp_context *psp,
mdelay(20); mdelay(20);
/* Wait for response flag (bit 31) in C2PMSG_64 */ /* Wait for response flag (bit 31) in C2PMSG_64 */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), ret = psp_wait_for(
0x80000000, 0x8000FFFF, false); psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
} }
return ret; return ret;

25
drivers/gpu/drm/amd/amdgpu/psp_v14_0.c
View file

@ -248,8 +248,9 @@ static int psp_v14_0_ring_stop(struct psp_context *psp,
/* there might be handshake issue with hardware which needs delay */ /* there might be handshake issue with hardware which needs delay */
mdelay(20); mdelay(20);
/* Wait for response flag (bit 31) */ /* Wait for response flag (bit 31) */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), ret = psp_wait_for(
0x80000000, 0x80000000, false); psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
} else { } else {
/* Write the ring destroy command*/ /* Write the ring destroy command*/
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64,
@ -257,8 +258,9 @@ static int psp_v14_0_ring_stop(struct psp_context *psp,
/* there might be handshake issue with hardware which needs delay */ /* there might be handshake issue with hardware which needs delay */
mdelay(20); mdelay(20);
/* Wait for response flag (bit 31) */ /* Wait for response flag (bit 31) */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), ret = psp_wait_for(
0x80000000, 0x80000000, false); psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
} }
return ret; return ret;
@ -294,13 +296,15 @@ static int psp_v14_0_ring_create(struct psp_context *psp,
mdelay(20); mdelay(20);
/* Wait for response flag (bit 31) in C2PMSG_101 */ /* Wait for response flag (bit 31) in C2PMSG_101 */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), ret = psp_wait_for(
0x80000000, 0x8000FFFF, false); psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
} else { } else {
/* Wait for sOS ready for ring creation */ /* Wait for sOS ready for ring creation */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), ret = psp_wait_for(
0x80000000, 0x80000000, false); psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
if (ret) { if (ret) {
DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
return ret; return ret;
@ -324,8 +328,9 @@ static int psp_v14_0_ring_create(struct psp_context *psp,
mdelay(20); mdelay(20);
/* Wait for response flag (bit 31) in C2PMSG_64 */ /* Wait for response flag (bit 31) in C2PMSG_64 */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), ret = psp_wait_for(
0x80000000, 0x8000FFFF, false); psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
} }
return ret; return ret;