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drm/sun4i: support TCONs without channel 1

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Some Allwinner SoCs, such as the A33, have a variation of the TCON that
doesn't have a second channel (or it is not wired to anything).

Make sure we can handle that case.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
This commit is contained in:
Maxime Ripard 2016-01-07 12:32:07 +01:00
parent b5644a5e72
commit 8e92404725
2 changed files with 23 additions and 13 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

34
drivers/gpu/drm/sun4i/sun4i_tcon.c
View file

@ -59,11 +59,13 @@ void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int channel)
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
SUN4I_TCON0_CTL_TCON_ENABLE, 0); SUN4I_TCON0_CTL_TCON_ENABLE, 0);
clk_disable_unprepare(tcon->dclk); clk_disable_unprepare(tcon->dclk);
} else if (channel == 1) { return;
regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
SUN4I_TCON1_CTL_TCON_ENABLE, 0);
clk_disable_unprepare(tcon->sclk1);
} }
WARN_ON(!tcon->has_channel_1);
regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
SUN4I_TCON1_CTL_TCON_ENABLE, 0);
clk_disable_unprepare(tcon->sclk1);
} }
EXPORT_SYMBOL(sun4i_tcon_channel_disable); EXPORT_SYMBOL(sun4i_tcon_channel_disable);
@ -75,12 +77,14 @@ void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel)
SUN4I_TCON0_CTL_TCON_ENABLE, SUN4I_TCON0_CTL_TCON_ENABLE,
SUN4I_TCON0_CTL_TCON_ENABLE); SUN4I_TCON0_CTL_TCON_ENABLE);
clk_prepare_enable(tcon->dclk); clk_prepare_enable(tcon->dclk);
} else if (channel == 1) { return;
regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
SUN4I_TCON1_CTL_TCON_ENABLE,
SUN4I_TCON1_CTL_TCON_ENABLE);
clk_prepare_enable(tcon->sclk1);
} }
WARN_ON(!tcon->has_channel_1);
regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
SUN4I_TCON1_CTL_TCON_ENABLE,
SUN4I_TCON1_CTL_TCON_ENABLE);
clk_prepare_enable(tcon->sclk1);
} }
EXPORT_SYMBOL(sun4i_tcon_channel_enable); EXPORT_SYMBOL(sun4i_tcon_channel_enable);
@ -198,6 +202,8 @@ void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
u8 clk_delay; u8 clk_delay;
u32 val; u32 val;
WARN_ON(!tcon->has_channel_1);
/* Adjust clock delay */ /* Adjust clock delay */
clk_delay = sun4i_tcon_get_clk_delay(mode, 1); clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
@ -321,10 +327,12 @@ static int sun4i_tcon_init_clocks(struct device *dev,
return PTR_ERR(tcon->sclk0); return PTR_ERR(tcon->sclk0);
} }
tcon->sclk1 = devm_clk_get(dev, "tcon-ch1"); if (tcon->has_channel_1) {
if (IS_ERR(tcon->sclk1)) { tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
dev_err(dev, "Couldn't get the TCON channel 1 clock\n"); if (IS_ERR(tcon->sclk1)) {
return PTR_ERR(tcon->sclk1); dev_err(dev, "Couldn't get the TCON channel 1 clock\n");
return PTR_ERR(tcon->sclk1);
}
} }
return sun4i_dclk_create(dev, tcon); return sun4i_dclk_create(dev, tcon);

2
drivers/gpu/drm/sun4i/sun4i_tcon.h
View file

@ -164,6 +164,8 @@ struct sun4i_tcon {
bool has_mux; bool has_mux;
struct drm_panel *panel; struct drm_panel *panel;
bool has_channel_1;
}; };
struct drm_bridge *sun4i_tcon_find_bridge(struct device_node *node); struct drm_bridge *sun4i_tcon_find_bridge(struct device_node *node);