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	clk: mvebu: dove: maintain clock init order
Init order of CLK_OF_DECLARE'd drivers depends on compile order. Unfortunately, clk_of_init does not allow drivers to return errors, e.g. -EPROBE_DEFER if parent clocks have not been registered, yet. To avoid init order woes for MVEBU clock drivers, we take care of proper init order ourselves. This patch joins core-clk and gating-clk init to maintain proper init order. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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					 1 changed files with 9 additions and 10 deletions
				
			
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			@ -154,12 +154,6 @@ static const struct coreclk_soc_desc dove_coreclks = {
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	.num_ratios = ARRAY_SIZE(dove_coreclk_ratios),
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};
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static void __init dove_coreclk_init(struct device_node *np)
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{
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	mvebu_coreclk_setup(np, &dove_coreclks);
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}
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CLK_OF_DECLARE(dove_core_clk, "marvell,dove-core-clock", dove_coreclk_init);
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/*
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 * Clock Gating Control
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 */
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			@ -186,9 +180,14 @@ static const struct clk_gating_soc_desc dove_gating_desc[] __initconst = {
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	{ }
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};
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static void __init dove_clk_gating_init(struct device_node *np)
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static void __init dove_clk_init(struct device_node *np)
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{
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	mvebu_clk_gating_setup(np, dove_gating_desc);
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	struct device_node *cgnp =
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		of_find_compatible_node(NULL, NULL, "marvell,dove-gating-clock");
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	mvebu_coreclk_setup(np, &dove_coreclks);
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	if (cgnp)
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		mvebu_clk_gating_setup(cgnp, dove_gating_desc);
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}
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CLK_OF_DECLARE(dove_clk_gating, "marvell,dove-gating-clock",
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	       dove_clk_gating_init);
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CLK_OF_DECLARE(dove_clk, "marvell,dove-core-clock", dove_clk_init);
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