mirrors/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2025-11-04 02:30:34 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions

dt-bindings: clock: Introduce QCOM LPASS clock bindings

Browse source 
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Taniya Das 2018-11-30 23:51:28 +05:30 committed by Stephen Boyd
parent 7898e4fef8
commit 8ff1a156cb
4 changed files with 46 additions and 1 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

4
Documentation/devicetree/bindings/clock/qcom,gcc.txt
View file

@ -67,5 +67,7 @@ Example of GCC with protected-clocks properties:
#power-domain-cells = <1>; #power-domain-cells = <1>;
protected-clocks = <GCC_QSPI_CORE_CLK>, protected-clocks = <GCC_QSPI_CORE_CLK>,
<GCC_QSPI_CORE_CLK_SRC>, <GCC_QSPI_CORE_CLK_SRC>,
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>; <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<GCC_LPASS_Q6_AXI_CLK>,
<GCC_LPASS_SWAY_CLK>;
}; };

26
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt Normal file
View file

@ -0,0 +1,26 @@
Qualcomm LPASS Clock Controller Binding
-----------------------------------------------
Required properties :
- compatible : shall contain "qcom,sdm845-lpasscc"
- #clock-cells : from common clock binding, shall contain 1.
- reg : shall contain base register address and size,
in the order
Index-0 maps to LPASS_CC register region
Index-1 maps to LPASS_QDSP6SS register region
Optional properties :
- reg-names : register names of LPASS domain
"cc", "qdsp6ss".
Example:
The below node has to be defined in the cases where the LPASS peripheral loader
would bring the subsystem out of reset.
lpasscc: clock-controller@17014000 {
compatible = "qcom,sdm845-lpasscc";
reg = <0x17014000 0x1f004>, <0x17300000 0x200>;
reg-names = "cc", "qdsp6ss";
#clock-cells = <1>;
};

2
include/dt-bindings/clock/qcom,gcc-sdm845.h
View file

@ -197,6 +197,8 @@
#define GCC_QSPI_CORE_CLK_SRC 187 #define GCC_QSPI_CORE_CLK_SRC 187
#define GCC_QSPI_CORE_CLK 188 #define GCC_QSPI_CORE_CLK 188
#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 #define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189
#define GCC_LPASS_Q6_AXI_CLK 190
#define GCC_LPASS_SWAY_CLK 191
/* GCC Resets */ /* GCC Resets */
#define GCC_MMSS_BCR 0 #define GCC_MMSS_BCR 0

15
include/dt-bindings/clock/qcom,lpass-sdm845.h Normal file
View file

@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H
#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H
#define LPASS_Q6SS_AHBM_AON_CLK 0
#define LPASS_Q6SS_AHBS_AON_CLK 1
#define LPASS_QDSP6SS_XO_CLK 2
#define LPASS_QDSP6SS_SLEEP_CLK 3
#define LPASS_QDSP6SS_CORE_CLK 4
#endif