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https://github.com/torvalds/linux.git
synced 2025-11-04 10:40:15 +02:00
spi: spi-fsl-dspi: Add DMA support for Vybrid
Add DMA support for Vybrid. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Sanchayan Maity
Mark Brown
parent
1001354ca3
commit
90ba37033c
1 changed files with 300 additions and 1 deletions
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@ -15,6 +15,8 @@
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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@ -40,6 +42,7 @@
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#define TRAN_STATE_WORD_ODD_NUM 0x04
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#define DSPI_FIFO_SIZE 4
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#define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024)
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#define SPI_MCR 0x00
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#define SPI_MCR_MASTER (1 << 31)
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@ -71,6 +74,11 @@
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#define SPI_SR_EOQF 0x10000000
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#define SPI_SR_TCFQF 0x80000000
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#define SPI_RSER_TFFFE BIT(25)
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#define SPI_RSER_TFFFD BIT(24)
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#define SPI_RSER_RFDFE BIT(17)
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#define SPI_RSER_RFDFD BIT(16)
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#define SPI_RSER 0x30
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#define SPI_RSER_EOQFE 0x10000000
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#define SPI_RSER_TCFQE 0x80000000
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@ -108,6 +116,8 @@
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#define SPI_TCR_TCNT_MAX 0x10000
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#define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
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struct chip_data {
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u32 mcr_val;
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u32 ctar_val;
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@ -117,6 +127,7 @@ struct chip_data {
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enum dspi_trans_mode {
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DSPI_EOQ_MODE = 0,
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DSPI_TCFQ_MODE,
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DSPI_DMA_MODE,
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};
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struct fsl_dspi_devtype_data {
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@ -125,7 +136,7 @@ struct fsl_dspi_devtype_data {
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};
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static const struct fsl_dspi_devtype_data vf610_data = {
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.trans_mode = DSPI_EOQ_MODE,
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.trans_mode = DSPI_DMA_MODE,
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.max_clock_factor = 2,
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};
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@ -139,6 +150,22 @@ static const struct fsl_dspi_devtype_data ls2085a_data = {
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.max_clock_factor = 8,
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};
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struct fsl_dspi_dma {
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u32 curr_xfer_len;
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u32 *tx_dma_buf;
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struct dma_chan *chan_tx;
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dma_addr_t tx_dma_phys;
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struct completion cmd_tx_complete;
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struct dma_async_tx_descriptor *tx_desc;
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u32 *rx_dma_buf;
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struct dma_chan *chan_rx;
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dma_addr_t rx_dma_phys;
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struct completion cmd_rx_complete;
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struct dma_async_tx_descriptor *rx_desc;
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};
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struct fsl_dspi {
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struct spi_master *master;
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struct platform_device *pdev;
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@ -165,6 +192,7 @@ struct fsl_dspi {
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u32 waitflags;
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u32 spi_tcnt;
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struct fsl_dspi_dma *dma;
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};
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static inline int is_double_byte_mode(struct fsl_dspi *dspi)
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@ -176,6 +204,263 @@ static inline int is_double_byte_mode(struct fsl_dspi *dspi)
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return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
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}
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static void dspi_tx_dma_callback(void *arg)
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{
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struct fsl_dspi *dspi = arg;
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struct fsl_dspi_dma *dma = dspi->dma;
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complete(&dma->cmd_tx_complete);
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}
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static void dspi_rx_dma_callback(void *arg)
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{
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struct fsl_dspi *dspi = arg;
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struct fsl_dspi_dma *dma = dspi->dma;
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int rx_word;
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int i, len;
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u16 d;
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rx_word = is_double_byte_mode(dspi);
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len = rx_word ? (dma->curr_xfer_len / 2) : dma->curr_xfer_len;
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if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) {
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for (i = 0; i < len; i++) {
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d = dspi->dma->rx_dma_buf[i];
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rx_word ? (*(u16 *)dspi->rx = d) :
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(*(u8 *)dspi->rx = d);
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dspi->rx += rx_word + 1;
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}
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}
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complete(&dma->cmd_rx_complete);
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}
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static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
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{
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struct fsl_dspi_dma *dma = dspi->dma;
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struct device *dev = &dspi->pdev->dev;
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int time_left;
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int tx_word;
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int i, len;
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u16 val;
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tx_word = is_double_byte_mode(dspi);
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len = tx_word ? (dma->curr_xfer_len / 2) : dma->curr_xfer_len;
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for (i = 0; i < len - 1; i++) {
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val = tx_word ? *(u16 *) dspi->tx : *(u8 *) dspi->tx;
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dspi->dma->tx_dma_buf[i] =
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SPI_PUSHR_TXDATA(val) | SPI_PUSHR_PCS(dspi->cs) |
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SPI_PUSHR_CTAS(0) | SPI_PUSHR_CONT;
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dspi->tx += tx_word + 1;
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}
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val = tx_word ? *(u16 *) dspi->tx : *(u8 *) dspi->tx;
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dspi->dma->tx_dma_buf[i] = SPI_PUSHR_TXDATA(val) |
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SPI_PUSHR_PCS(dspi->cs) |
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SPI_PUSHR_CTAS(0);
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dspi->tx += tx_word + 1;
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dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
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dma->tx_dma_phys,
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DSPI_DMA_BUFSIZE, DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!dma->tx_desc) {
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dev_err(dev, "Not able to get desc for DMA xfer\n");
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return -EIO;
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}
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dma->tx_desc->callback = dspi_tx_dma_callback;
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dma->tx_desc->callback_param = dspi;
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if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
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dev_err(dev, "DMA submit failed\n");
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return -EINVAL;
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}
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dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
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dma->rx_dma_phys,
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DSPI_DMA_BUFSIZE, DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!dma->rx_desc) {
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dev_err(dev, "Not able to get desc for DMA xfer\n");
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return -EIO;
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}
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dma->rx_desc->callback = dspi_rx_dma_callback;
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dma->rx_desc->callback_param = dspi;
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if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
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dev_err(dev, "DMA submit failed\n");
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return -EINVAL;
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}
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reinit_completion(&dspi->dma->cmd_rx_complete);
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reinit_completion(&dspi->dma->cmd_tx_complete);
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dma_async_issue_pending(dma->chan_rx);
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dma_async_issue_pending(dma->chan_tx);
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time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
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DMA_COMPLETION_TIMEOUT);
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if (time_left == 0) {
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dev_err(dev, "DMA tx timeout\n");
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dmaengine_terminate_all(dma->chan_tx);
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dmaengine_terminate_all(dma->chan_rx);
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return -ETIMEDOUT;
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}
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time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
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DMA_COMPLETION_TIMEOUT);
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if (time_left == 0) {
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dev_err(dev, "DMA rx timeout\n");
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dmaengine_terminate_all(dma->chan_tx);
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dmaengine_terminate_all(dma->chan_rx);
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int dspi_dma_xfer(struct fsl_dspi *dspi)
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{
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struct fsl_dspi_dma *dma = dspi->dma;
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struct device *dev = &dspi->pdev->dev;
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int curr_remaining_bytes;
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int bytes_per_buffer;
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int tx_word;
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int ret = 0;
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tx_word = is_double_byte_mode(dspi);
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curr_remaining_bytes = dspi->len;
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while (curr_remaining_bytes) {
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/* Check if current transfer fits the DMA buffer */
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dma->curr_xfer_len = curr_remaining_bytes;
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bytes_per_buffer = DSPI_DMA_BUFSIZE /
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(DSPI_FIFO_SIZE / (tx_word ? 2 : 1));
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if (curr_remaining_bytes > bytes_per_buffer)
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dma->curr_xfer_len = bytes_per_buffer;
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ret = dspi_next_xfer_dma_submit(dspi);
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if (ret) {
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dev_err(dev, "DMA transfer failed\n");
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goto exit;
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} else {
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curr_remaining_bytes -= dma->curr_xfer_len;
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if (curr_remaining_bytes < 0)
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curr_remaining_bytes = 0;
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dspi->len = curr_remaining_bytes;
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}
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}
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exit:
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return ret;
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}
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static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
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{
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struct fsl_dspi_dma *dma;
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struct dma_slave_config cfg;
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struct device *dev = &dspi->pdev->dev;
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int ret;
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dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
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if (!dma)
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return -ENOMEM;
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dma->chan_rx = dma_request_slave_channel(dev, "rx");
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if (!dma->chan_rx) {
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dev_err(dev, "rx dma channel not available\n");
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ret = -ENODEV;
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return ret;
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}
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dma->chan_tx = dma_request_slave_channel(dev, "tx");
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if (!dma->chan_tx) {
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dev_err(dev, "tx dma channel not available\n");
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ret = -ENODEV;
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goto err_tx_channel;
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}
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dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
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&dma->tx_dma_phys, GFP_KERNEL);
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if (!dma->tx_dma_buf) {
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ret = -ENOMEM;
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goto err_tx_dma_buf;
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}
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dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
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&dma->rx_dma_phys, GFP_KERNEL);
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if (!dma->rx_dma_buf) {
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ret = -ENOMEM;
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goto err_rx_dma_buf;
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}
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cfg.src_addr = phy_addr + SPI_POPR;
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cfg.dst_addr = phy_addr + SPI_PUSHR;
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cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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cfg.src_maxburst = 1;
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cfg.dst_maxburst = 1;
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cfg.direction = DMA_DEV_TO_MEM;
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ret = dmaengine_slave_config(dma->chan_rx, &cfg);
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if (ret) {
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dev_err(dev, "can't configure rx dma channel\n");
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ret = -EINVAL;
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goto err_slave_config;
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}
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cfg.direction = DMA_MEM_TO_DEV;
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ret = dmaengine_slave_config(dma->chan_tx, &cfg);
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if (ret) {
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dev_err(dev, "can't configure tx dma channel\n");
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ret = -EINVAL;
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goto err_slave_config;
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}
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dspi->dma = dma;
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init_completion(&dma->cmd_tx_complete);
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init_completion(&dma->cmd_rx_complete);
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return 0;
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err_slave_config:
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devm_kfree(dev, dma->rx_dma_buf);
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err_rx_dma_buf:
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devm_kfree(dev, dma->tx_dma_buf);
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err_tx_dma_buf:
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dma_release_channel(dma->chan_tx);
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err_tx_channel:
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dma_release_channel(dma->chan_rx);
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devm_kfree(dev, dma);
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dspi->dma = NULL;
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return ret;
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}
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static void dspi_release_dma(struct fsl_dspi *dspi)
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{
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struct fsl_dspi_dma *dma = dspi->dma;
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struct device *dev = &dspi->pdev->dev;
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if (dma) {
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if (dma->chan_tx) {
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dma_unmap_single(dev, dma->tx_dma_phys,
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DSPI_DMA_BUFSIZE, DMA_TO_DEVICE);
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dma_release_channel(dma->chan_tx);
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}
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if (dma->chan_rx) {
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dma_unmap_single(dev, dma->rx_dma_phys,
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DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE);
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dma_release_channel(dma->chan_rx);
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}
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}
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}
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static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
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unsigned long clkrate)
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{
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@ -424,6 +709,12 @@ static int dspi_transfer_one_message(struct spi_master *master,
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regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE);
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dspi_tcfq_write(dspi);
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break;
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case DSPI_DMA_MODE:
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regmap_write(dspi->regmap, SPI_RSER,
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SPI_RSER_TFFFE | SPI_RSER_TFFFD |
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SPI_RSER_RFDFE | SPI_RSER_RFDFD);
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status = dspi_dma_xfer(dspi);
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goto out;
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default:
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dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
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trans_mode);
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@ -733,6 +1024,13 @@ static int dspi_probe(struct platform_device *pdev)
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if (ret)
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goto out_master_put;
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if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
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if (dspi_request_dma(dspi, res->start)) {
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dev_err(&pdev->dev, "can't get dma channels\n");
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goto out_clk_put;
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}
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}
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master->max_speed_hz =
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clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
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@ -761,6 +1059,7 @@ static int dspi_remove(struct platform_device *pdev)
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struct fsl_dspi *dspi = spi_master_get_devdata(master);
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/* Disconnect from the SPI framework */
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dspi_release_dma(dspi);
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clk_disable_unprepare(dspi->clk);
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spi_unregister_master(dspi->master);
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