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PM / devfreq: rk3399_dmc: Pass ODT and auto power down parameters to TF-A.
Trusted Firmware-A (TF-A) for rk3399 implements a SiP call to get the on-die termination (ODT) and auto power down parameters from kernel, this patch adds the functionality to do this. Also, if DDR clock frequency is lower than the on-die termination (ODT) disable frequency this driver should disable the DDR ODT. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Gaël PORTAY <gael.portay@collabora.com> Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
This commit is contained in:
Enric Balletbo i Serra
MyungJoo Ham
parent
adfe3b7660
commit
9173c5ceb0
2 changed files with 71 additions and 1 deletions
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@ -18,14 +18,17 @@
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#include <linux/devfreq.h>
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#include <linux/devfreq-event.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/rwsem.h>
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#include <linux/suspend.h>
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#include <soc/rockchip/rk3399_grf.h>
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#include <soc/rockchip/rockchip_sip.h>
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struct dram_timing {
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@ -69,8 +72,11 @@ struct rk3399_dmcfreq {
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struct mutex lock;
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struct dram_timing timing;
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struct regulator *vdd_center;
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struct regmap *regmap_pmu;
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unsigned long rate, target_rate;
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unsigned long volt, target_volt;
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unsigned int odt_dis_freq;
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int odt_pd_arg0, odt_pd_arg1;
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};
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static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
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@ -80,6 +86,8 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
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struct dev_pm_opp *opp;
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unsigned long old_clk_rate = dmcfreq->rate;
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unsigned long target_volt, target_rate;
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struct arm_smccc_res res;
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bool odt_enable = false;
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int err;
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opp = devfreq_recommended_opp(dev, freq, flags);
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@ -95,6 +103,19 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
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mutex_lock(&dmcfreq->lock);
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if (target_rate >= dmcfreq->odt_dis_freq)
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odt_enable = true;
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/*
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* This makes a SMC call to the TF-A to set the DDR PD (power-down)
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* timings and to enable or disable the ODT (on-die termination)
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* resistors.
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*/
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arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0,
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dmcfreq->odt_pd_arg1,
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ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD,
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odt_enable, 0, 0, 0, &res);
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/*
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* If frequency scaling from low to high, adjust voltage first.
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* If frequency scaling from high to low, adjust frequency first.
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@ -294,11 +315,13 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
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{
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struct arm_smccc_res res;
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struct device *dev = &pdev->dev;
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struct device_node *np = pdev->dev.of_node;
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struct device_node *np = pdev->dev.of_node, *node;
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struct rk3399_dmcfreq *data;
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int ret, index, size;
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uint32_t *timing;
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struct dev_pm_opp *opp;
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u32 ddr_type;
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u32 val;
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data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
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if (!data)
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@ -354,10 +377,56 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
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}
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}
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node = of_parse_phandle(np, "rockchip,pmu", 0);
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if (node) {
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data->regmap_pmu = syscon_node_to_regmap(node);
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if (IS_ERR(data->regmap_pmu))
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return PTR_ERR(data->regmap_pmu);
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}
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regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
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ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
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RK3399_PMUGRF_DDRTYPE_MASK;
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switch (ddr_type) {
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case RK3399_PMUGRF_DDRTYPE_DDR3:
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data->odt_dis_freq = data->timing.ddr3_odt_dis_freq;
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break;
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case RK3399_PMUGRF_DDRTYPE_LPDDR3:
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data->odt_dis_freq = data->timing.lpddr3_odt_dis_freq;
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break;
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case RK3399_PMUGRF_DDRTYPE_LPDDR4:
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data->odt_dis_freq = data->timing.lpddr4_odt_dis_freq;
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break;
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default:
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return -EINVAL;
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};
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arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
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ROCKCHIP_SIP_CONFIG_DRAM_INIT,
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0, 0, 0, 0, &res);
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/*
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* In TF-A there is a platform SIP call to set the PD (power-down)
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* timings and to enable or disable the ODT (on-die termination).
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* This call needs three arguments as follows:
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*
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* arg0:
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* bit[0-7] : sr_idle
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* bit[8-15] : sr_mc_gate_idle
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* bit[16-31] : standby idle
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* arg1:
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* bit[0-11] : pd_idle
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* bit[16-27] : srpd_lite_idle
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* arg2:
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* bit[0] : odt enable
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*/
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data->odt_pd_arg0 = (data->timing.sr_idle & 0xff) |
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((data->timing.sr_mc_gate_idle & 0xff) << 8) |
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((data->timing.standby_idle & 0xffff) << 16);
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data->odt_pd_arg1 = (data->timing.pd_idle & 0xfff) |
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((data->timing.srpd_lite_idle & 0xfff) << 16);
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/*
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* We add a devfreq driver to our parent since it has a device tree node
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* with operating points.
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@ -23,5 +23,6 @@
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#define ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE 0x05
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#define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06
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#define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07
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#define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08
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#endif
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