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drm/amdgpu: Introduce funcs for populating CPER
Introduce utility functions designed to assist in populating CPER records. v2: call cper_init/fini in device_ip_init/fini. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang
Alex Deucher
parent
523b69c654
commit
92d5d2a09d
5 changed files with 382 additions and 1 deletions
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@ -65,7 +65,8 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \
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amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
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amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
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amdgpu_fw_attestation.o amdgpu_securedisplay.o \
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amdgpu_fw_attestation.o amdgpu_securedisplay.o \
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amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \
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amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \
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amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_aca.o amdgpu_dev_coredump.o
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amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_aca.o amdgpu_dev_coredump.o \
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amdgpu_cper.o
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amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
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amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
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@ -109,6 +109,7 @@
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#include "amdgpu_mca.h"
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#include "amdgpu_mca.h"
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#include "amdgpu_aca.h"
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#include "amdgpu_aca.h"
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#include "amdgpu_ras.h"
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#include "amdgpu_ras.h"
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#include "amdgpu_cper.h"
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#include "amdgpu_xcp.h"
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#include "amdgpu_xcp.h"
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#include "amdgpu_seq64.h"
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#include "amdgpu_seq64.h"
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#include "amdgpu_reg_state.h"
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#include "amdgpu_reg_state.h"
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@ -1091,6 +1092,9 @@ struct amdgpu_device {
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/* ACA */
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/* ACA */
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struct amdgpu_aca aca;
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struct amdgpu_aca aca;
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/* CPER */
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struct amdgpu_cper cper;
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struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
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struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
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uint32_t harvest_ip_mask;
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uint32_t harvest_ip_mask;
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int num_ip_blocks;
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int num_ip_blocks;
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281
drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c
Normal file
281
drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c
Normal file
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@ -0,0 +1,281 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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static const guid_t MCE = CPER_NOTIFY_MCE;
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static const guid_t CMC = CPER_NOTIFY_CMC;
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static const guid_t BOOT = BOOT_TYPE;
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static const guid_t CRASHDUMP = AMD_CRASHDUMP;
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static const guid_t RUNTIME = AMD_GPU_NONSTANDARD_ERROR;
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static void __inc_entry_length(struct cper_hdr *hdr, uint32_t size)
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{
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hdr->record_length += size;
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}
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void amdgpu_cper_entry_fill_hdr(struct amdgpu_device *adev,
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struct cper_hdr *hdr,
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enum amdgpu_cper_type type,
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enum cper_error_severity sev)
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{
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hdr->signature[0] = 'C';
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hdr->signature[1] = 'P';
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hdr->signature[2] = 'E';
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hdr->signature[3] = 'R';
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hdr->revision = CPER_HDR_REV_1;
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hdr->signature_end = 0xFFFFFFFF;
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hdr->error_severity = sev;
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hdr->valid_bits.platform_id = 1;
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hdr->valid_bits.partition_id = 1;
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hdr->valid_bits.timestamp = 1;
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/*TODO need to initialize hdr->timestamp */
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snprintf(hdr->record_id, 8, "%d", atomic_inc_return(&adev->cper.unique_id));
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snprintf(hdr->platform_id, 16, "0x%04X:0x%04X",
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adev->pdev->vendor, adev->pdev->device);
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/* pmfw version should be part of creator_id according to CPER spec */
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snprintf(hdr->creator_id, 16, "%s", CPER_CREATOR_ID_AMDGPU);
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switch (type) {
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case AMDGPU_CPER_TYPE_BOOT:
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hdr->notify_type = BOOT;
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break;
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case AMDGPU_CPER_TYPE_FATAL:
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case AMDGPU_CPER_TYPE_BP_THRESHOLD:
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hdr->notify_type = MCE;
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break;
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case AMDGPU_CPER_TYPE_RUNTIME:
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if (sev == CPER_SEV_NON_FATAL_CORRECTED)
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hdr->notify_type = CMC;
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else
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hdr->notify_type = MCE;
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break;
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default:
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dev_err(adev->dev, "Unknown CPER Type\n");
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break;
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}
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__inc_entry_length(hdr, HDR_LEN);
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}
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static int amdgpu_cper_entry_fill_section_desc(struct amdgpu_device *adev,
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struct cper_sec_desc *section_desc,
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bool bp_threshold,
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bool poison,
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enum cper_error_severity sev,
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guid_t sec_type,
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uint32_t section_length,
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uint32_t section_offset)
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{
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section_desc->revision_minor = CPER_SEC_MINOR_REV_1;
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section_desc->revision_major = CPER_SEC_MAJOR_REV_22;
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section_desc->sec_offset = section_offset;
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section_desc->sec_length = section_length;
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section_desc->valid_bits.fru_id = 1;
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section_desc->valid_bits.fru_text = 1;
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section_desc->flag_bits.primary = 1;
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section_desc->severity = sev;
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section_desc->sec_type = sec_type;
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if (adev->smuio.funcs &&
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adev->smuio.funcs->get_socket_id)
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snprintf(section_desc->fru_text, 20, "OAM%d",
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adev->smuio.funcs->get_socket_id(adev));
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/* TODO: fru_id is 16 bytes in CPER spec, but driver defines it as 20 bytes */
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snprintf(section_desc->fru_id, 16, "%llx", adev->unique_id);
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if (bp_threshold)
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section_desc->flag_bits.exceed_err_threshold = 1;
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if (poison)
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section_desc->flag_bits.latent_err = 1;
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return 0;
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}
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int amdgpu_cper_entry_fill_fatal_section(struct amdgpu_device *adev,
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struct cper_hdr *hdr,
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uint32_t idx,
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struct cper_sec_crashdump_reg_data reg_data)
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{
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struct cper_sec_desc *section_desc;
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struct cper_sec_crashdump_fatal *section;
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section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx));
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section = (struct cper_sec_crashdump_fatal *)((uint8_t *)hdr +
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FATAL_SEC_OFFSET(hdr->sec_cnt, idx));
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amdgpu_cper_entry_fill_section_desc(adev, section_desc, false, false,
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CPER_SEV_FATAL, CRASHDUMP, FATAL_SEC_LEN,
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FATAL_SEC_OFFSET(hdr->sec_cnt, idx));
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section->body.reg_ctx_type = CPER_CTX_TYPE_CRASH;
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section->body.reg_arr_size = sizeof(reg_data);
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section->body.data = reg_data;
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__inc_entry_length(hdr, SEC_DESC_LEN + FATAL_SEC_LEN);
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return 0;
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}
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int amdgpu_cper_entry_fill_runtime_section(struct amdgpu_device *adev,
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struct cper_hdr *hdr,
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uint32_t idx,
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enum cper_error_severity sev,
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uint32_t *reg_dump,
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uint32_t reg_count)
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{
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struct cper_sec_desc *section_desc;
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struct cper_sec_nonstd_err *section;
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bool poison;
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poison = (sev == CPER_SEV_NON_FATAL_CORRECTED) ? false : true;
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section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx));
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section = (struct cper_sec_nonstd_err *)((uint8_t *)hdr +
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NONSTD_SEC_OFFSET(hdr->sec_cnt, idx));
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amdgpu_cper_entry_fill_section_desc(adev, section_desc, false, poison,
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sev, RUNTIME, NONSTD_SEC_LEN,
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NONSTD_SEC_OFFSET(hdr->sec_cnt, idx));
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reg_count = min(reg_count, CPER_ACA_REG_COUNT);
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section->hdr.valid_bits.err_info_cnt = 1;
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section->hdr.valid_bits.err_context_cnt = 1;
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section->info.error_type = RUNTIME;
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section->info.ms_chk_bits.err_type_valid = 1;
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section->ctx.reg_ctx_type = CPER_CTX_TYPE_CRASH;
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section->ctx.reg_arr_size = sizeof(section->ctx.reg_dump);
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memcpy(section->ctx.reg_dump, reg_dump, reg_count * sizeof(uint32_t));
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__inc_entry_length(hdr, SEC_DESC_LEN + NONSTD_SEC_LEN);
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return 0;
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}
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int amdgpu_cper_entry_fill_bad_page_threshold_section(struct amdgpu_device *adev,
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struct cper_hdr *hdr,
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uint32_t idx)
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{
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struct cper_sec_desc *section_desc;
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struct cper_sec_nonstd_err *section;
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section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx));
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section = (struct cper_sec_nonstd_err *)((uint8_t *)hdr +
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NONSTD_SEC_OFFSET(hdr->sec_cnt, idx));
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amdgpu_cper_entry_fill_section_desc(adev, section_desc, true, false,
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CPER_SEV_FATAL, RUNTIME, NONSTD_SEC_LEN,
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NONSTD_SEC_OFFSET(hdr->sec_cnt, idx));
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section->hdr.valid_bits.err_info_cnt = 1;
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section->hdr.valid_bits.err_context_cnt = 1;
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section->info.error_type = RUNTIME;
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section->info.ms_chk_bits.err_type_valid = 1;
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section->ctx.reg_ctx_type = CPER_CTX_TYPE_CRASH;
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section->ctx.reg_arr_size = sizeof(section->ctx.reg_dump);
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/* Hardcoded Reg dump for bad page threshold CPER */
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section->ctx.reg_dump[CPER_ACA_REG_CTL_LO] = 0x1;
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section->ctx.reg_dump[CPER_ACA_REG_CTL_HI] = 0x0;
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section->ctx.reg_dump[CPER_ACA_REG_STATUS_LO] = 0x137;
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section->ctx.reg_dump[CPER_ACA_REG_STATUS_HI] = 0xB0000000;
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section->ctx.reg_dump[CPER_ACA_REG_ADDR_LO] = 0x0;
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section->ctx.reg_dump[CPER_ACA_REG_ADDR_HI] = 0x0;
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section->ctx.reg_dump[CPER_ACA_REG_MISC0_LO] = 0x0;
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section->ctx.reg_dump[CPER_ACA_REG_MISC0_HI] = 0x0;
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section->ctx.reg_dump[CPER_ACA_REG_CONFIG_LO] = 0x2;
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section->ctx.reg_dump[CPER_ACA_REG_CONFIG_HI] = 0x1ff;
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section->ctx.reg_dump[CPER_ACA_REG_IPID_LO] = 0x0;
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section->ctx.reg_dump[CPER_ACA_REG_IPID_HI] = 0x96;
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section->ctx.reg_dump[CPER_ACA_REG_SYND_LO] = 0x0;
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section->ctx.reg_dump[CPER_ACA_REG_SYND_HI] = 0x0;
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__inc_entry_length(hdr, SEC_DESC_LEN + NONSTD_SEC_LEN);
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return 0;
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}
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struct cper_hdr *amdgpu_cper_alloc_entry(struct amdgpu_device *adev,
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enum amdgpu_cper_type type,
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uint16_t section_count)
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{
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struct cper_hdr *hdr;
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uint32_t size = 0;
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size += HDR_LEN;
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size += (SEC_DESC_LEN * section_count);
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switch (type) {
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case AMDGPU_CPER_TYPE_RUNTIME:
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case AMDGPU_CPER_TYPE_BP_THRESHOLD:
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size += (NONSTD_SEC_LEN * section_count);
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break;
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case AMDGPU_CPER_TYPE_FATAL:
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size += (FATAL_SEC_LEN * section_count);
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break;
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case AMDGPU_CPER_TYPE_BOOT:
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size += (BOOT_SEC_LEN * section_count);
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break;
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default:
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dev_err(adev->dev, "Unknown CPER Type!\n");
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return NULL;
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}
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hdr = kzalloc(size, GFP_KERNEL);
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if (!hdr)
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return NULL;
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/* Save this early */
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hdr->sec_cnt = section_count;
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return hdr;
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}
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int amdgpu_cper_init(struct amdgpu_device *adev)
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{
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mutex_init(&adev->cper.cper_lock);
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adev->cper.enabled = true;
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adev->cper.max_count = CPER_MAX_ALLOWED_COUNT;
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/*TODO: initialize cper ring*/
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return 0;
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}
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int amdgpu_cper_fini(struct amdgpu_device *adev)
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{
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adev->cper.enabled = false;
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/*TODO: free cper ring */
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adev->cper.count = 0;
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adev->cper.wptr = 0;
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return 0;
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}
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91
drivers/gpu/drm/amd/amdgpu/amdgpu_cper.h
Normal file
91
drivers/gpu/drm/amd/amdgpu/amdgpu_cper.h
Normal file
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@ -0,0 +1,91 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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||||||
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* to deal in the Software without restriction, including without limitation
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||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __AMDGPU_CPER_H__
|
||||||
|
#define __AMDGPU_CPER_H__
|
||||||
|
|
||||||
|
#include "amd_cper.h"
|
||||||
|
|
||||||
|
#define CPER_MAX_ALLOWED_COUNT 0x1000
|
||||||
|
#define HDR_LEN (sizeof(struct cper_hdr))
|
||||||
|
#define SEC_DESC_LEN (sizeof(struct cper_sec_desc))
|
||||||
|
|
||||||
|
#define BOOT_SEC_LEN (sizeof(struct cper_sec_crashdump_boot))
|
||||||
|
#define FATAL_SEC_LEN (sizeof(struct cper_sec_crashdump_fatal))
|
||||||
|
#define NONSTD_SEC_LEN (sizeof(struct cper_sec_nonstd_err))
|
||||||
|
|
||||||
|
#define SEC_DESC_OFFSET(idx) (HDR_LEN + (SEC_DESC_LEN * idx))
|
||||||
|
|
||||||
|
#define BOOT_SEC_OFFSET(count, idx) (HDR_LEN + (SEC_DESC_LEN * count) + (BOOT_SEC_LEN * idx))
|
||||||
|
#define FATAL_SEC_OFFSET(count, idx) (HDR_LEN + (SEC_DESC_LEN * count) + (FATAL_SEC_LEN * idx))
|
||||||
|
#define NONSTD_SEC_OFFSET(count, idx) (HDR_LEN + (SEC_DESC_LEN * count) + (NONSTD_SEC_LEN * idx))
|
||||||
|
|
||||||
|
enum amdgpu_cper_type {
|
||||||
|
AMDGPU_CPER_TYPE_RUNTIME,
|
||||||
|
AMDGPU_CPER_TYPE_FATAL,
|
||||||
|
AMDGPU_CPER_TYPE_BOOT,
|
||||||
|
AMDGPU_CPER_TYPE_BP_THRESHOLD,
|
||||||
|
};
|
||||||
|
|
||||||
|
struct amdgpu_cper {
|
||||||
|
bool enabled;
|
||||||
|
|
||||||
|
atomic_t unique_id;
|
||||||
|
struct mutex cper_lock;
|
||||||
|
|
||||||
|
/* Lifetime CPERs generated */
|
||||||
|
uint32_t count;
|
||||||
|
uint32_t max_count;
|
||||||
|
|
||||||
|
uint32_t wptr;
|
||||||
|
|
||||||
|
void *ring[CPER_MAX_ALLOWED_COUNT];
|
||||||
|
};
|
||||||
|
|
||||||
|
void amdgpu_cper_entry_fill_hdr(struct amdgpu_device *adev,
|
||||||
|
struct cper_hdr *hdr,
|
||||||
|
enum amdgpu_cper_type type,
|
||||||
|
enum cper_error_severity sev);
|
||||||
|
int amdgpu_cper_entry_fill_fatal_section(struct amdgpu_device *adev,
|
||||||
|
struct cper_hdr *hdr,
|
||||||
|
uint32_t idx,
|
||||||
|
struct cper_sec_crashdump_reg_data reg_data);
|
||||||
|
int amdgpu_cper_entry_fill_runtime_section(struct amdgpu_device *adev,
|
||||||
|
struct cper_hdr *hdr,
|
||||||
|
uint32_t idx,
|
||||||
|
enum cper_error_severity sev,
|
||||||
|
uint32_t *reg_dump,
|
||||||
|
uint32_t reg_count);
|
||||||
|
int amdgpu_cper_entry_fill_bad_page_threshold_section(struct amdgpu_device *adev,
|
||||||
|
struct cper_hdr *hdr,
|
||||||
|
uint32_t section_idx);
|
||||||
|
|
||||||
|
struct cper_hdr *amdgpu_cper_alloc_entry(struct amdgpu_device *adev,
|
||||||
|
enum amdgpu_cper_type type,
|
||||||
|
uint16_t section_count);
|
||||||
|
|
||||||
|
int amdgpu_cper_init(struct amdgpu_device *adev);
|
||||||
|
int amdgpu_cper_fini(struct amdgpu_device *adev);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -3091,6 +3091,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
|
||||||
|
|
||||||
amdgpu_fru_get_product_info(adev);
|
amdgpu_fru_get_product_info(adev);
|
||||||
|
|
||||||
|
r = amdgpu_cper_init(adev);
|
||||||
|
|
||||||
init_failed:
|
init_failed:
|
||||||
|
|
||||||
return r;
|
return r;
|
||||||
|
|
@ -3451,6 +3453,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
|
||||||
{
|
{
|
||||||
int i, r;
|
int i, r;
|
||||||
|
|
||||||
|
amdgpu_cper_fini(adev);
|
||||||
|
|
||||||
if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
|
if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
|
||||||
amdgpu_virt_release_ras_err_handler_data(adev);
|
amdgpu_virt_release_ras_err_handler_data(adev);
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue