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mailbox: imx: support i.MX8ULP S4 MU
Like i.MX8 SCU, i.MX8ULP S4 also has vendor specific protocol. - bind SCU/S4 MU part to share one tx/rx/init API to make code simple. - S4 msg max size is very large, so alloc the space at driver probe, not use local on stack variable. - S4 MU has 8 TR and 4 RR which is different with i.MX8 MU, so adapt code to reflect this. Tested on i.MX8MP, i.MX8ULP Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
This commit is contained in:
Peng Fan
Jassi Brar
parent
a6daa22073
commit
97961f78e8
2 changed files with 107 additions and 37 deletions
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@ -5,6 +5,7 @@
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#include <linux/clk.h>
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#include <linux/firmware/imx/ipc.h>
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#include <linux/firmware/imx/s4.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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@ -18,6 +19,8 @@
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#define IMX_MU_CHANS 16
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/* TX0/RX0/RXDB[0-3] */
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#define IMX_MU_SCU_CHANS 6
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/* TX0/RX0 */
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#define IMX_MU_S4_CHANS 2
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#define IMX_MU_CHAN_NAME_SIZE 20
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enum imx_mu_chan_type {
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@ -47,6 +50,11 @@ struct imx_sc_rpc_msg_max {
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u32 data[7];
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};
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struct imx_s4_rpc_msg_max {
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struct imx_s4_rpc_msg hdr;
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u32 data[254];
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};
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struct imx_mu_con_priv {
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unsigned int idx;
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char irq_desc[IMX_MU_CHAN_NAME_SIZE];
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@ -58,6 +66,7 @@ struct imx_mu_con_priv {
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struct imx_mu_priv {
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struct device *dev;
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void __iomem *base;
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void *msg;
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spinlock_t xcr_lock; /* control register lock */
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struct mbox_controller mbox;
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@ -75,7 +84,8 @@ struct imx_mu_priv {
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enum imx_mu_type {
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IMX_MU_V1,
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IMX_MU_V2,
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IMX_MU_V2 = BIT(1),
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IMX_MU_V2_S4 = BIT(15),
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};
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struct imx_mu_dcfg {
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@ -89,18 +99,18 @@ struct imx_mu_dcfg {
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u32 xCR[4]; /* Control Registers */
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};
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#define IMX_MU_xSR_GIPn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
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#define IMX_MU_xSR_RFn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
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#define IMX_MU_xSR_TEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
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#define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
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#define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
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#define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
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/* General Purpose Interrupt Enable */
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#define IMX_MU_xCR_GIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
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#define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
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/* Receive Interrupt Enable */
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#define IMX_MU_xCR_RIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
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#define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
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/* Transmit Interrupt Enable */
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#define IMX_MU_xCR_TIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
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#define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
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/* General Purpose Interrupt Request */
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#define IMX_MU_xCR_GIRn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
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#define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
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static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
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@ -167,14 +177,22 @@ static int imx_mu_generic_rx(struct imx_mu_priv *priv,
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return 0;
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}
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static int imx_mu_scu_tx(struct imx_mu_priv *priv,
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struct imx_mu_con_priv *cp,
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void *data)
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static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data)
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{
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struct imx_sc_rpc_msg_max *msg = data;
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u32 *arg = data;
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int i, ret;
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u32 xsr;
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u32 size, max_size, num_tr;
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if (priv->dcfg->type & IMX_MU_V2_S4) {
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size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size;
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max_size = sizeof(struct imx_s4_rpc_msg_max);
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num_tr = 8;
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} else {
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size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size;
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max_size = sizeof(struct imx_sc_rpc_msg_max);
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num_tr = 4;
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}
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switch (cp->type) {
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case IMX_MU_TYPE_TX:
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@ -183,27 +201,27 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
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* sizeof yields bytes.
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*/
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if (msg->hdr.size > sizeof(*msg) / 4) {
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if (size > max_size / 4) {
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/*
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* The real message size can be different to
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* struct imx_sc_rpc_msg_max size
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* struct imx_sc_rpc_msg_max/imx_s4_rpc_msg_max size
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*/
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dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on TX; got: %i bytes\n", sizeof(*msg), msg->hdr.size << 2);
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dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on TX; got: %i bytes\n", max_size, size << 2);
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return -EINVAL;
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}
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for (i = 0; i < 4 && i < msg->hdr.size; i++)
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imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
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for (; i < msg->hdr.size; i++) {
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for (i = 0; i < num_tr && i < size; i++)
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imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
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for (; i < size; i++) {
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ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],
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xsr,
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xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % 4),
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xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr),
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0, 100);
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if (ret) {
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dev_err(priv->dev, "Send data index: %d timeout\n", i);
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return ret;
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}
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imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
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imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
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}
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imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
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@ -216,23 +234,32 @@ static int imx_mu_scu_tx(struct imx_mu_priv *priv,
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return 0;
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}
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static int imx_mu_scu_rx(struct imx_mu_priv *priv,
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struct imx_mu_con_priv *cp)
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static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)
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{
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struct imx_sc_rpc_msg_max msg;
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u32 *data = (u32 *)&msg;
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u32 *data;
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int i, ret;
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u32 xsr;
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u32 size, max_size;
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data = (u32 *)priv->msg;
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imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));
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*data++ = imx_mu_read(priv, priv->dcfg->xRR);
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if (msg.hdr.size > sizeof(msg) / 4) {
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dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2);
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if (priv->dcfg->type & IMX_MU_V2_S4) {
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size = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size;
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max_size = sizeof(struct imx_s4_rpc_msg_max);
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} else {
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size = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size;
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max_size = sizeof(struct imx_sc_rpc_msg_max);
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}
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if (size > max_size / 4) {
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dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on RX; got: %i bytes\n", max_size, size << 2);
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return -EINVAL;
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}
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for (i = 1; i < msg.hdr.size; i++) {
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for (i = 1; i < size; i++) {
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ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
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xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0, 100);
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if (ret) {
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@ -243,7 +270,7 @@ static int imx_mu_scu_rx(struct imx_mu_priv *priv,
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}
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imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
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mbox_chan_received_data(cp->chan, (void *)&msg);
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mbox_chan_received_data(cp->chan, (void *)priv->msg);
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return 0;
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}
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@ -394,8 +421,8 @@ static const struct mbox_chan_ops imx_mu_ops = {
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.shutdown = imx_mu_shutdown,
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};
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static struct mbox_chan *imx_mu_scu_xlate(struct mbox_controller *mbox,
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const struct of_phandle_args *sp)
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static struct mbox_chan *imx_mu_specific_xlate(struct mbox_controller *mbox,
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const struct of_phandle_args *sp)
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{
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u32 type, idx, chan;
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@ -478,11 +505,12 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv)
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imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
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}
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static void imx_mu_init_scu(struct imx_mu_priv *priv)
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static void imx_mu_init_specific(struct imx_mu_priv *priv)
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{
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unsigned int i;
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int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS;
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for (i = 0; i < IMX_MU_SCU_CHANS; i++) {
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for (i = 0; i < num_chans; i++) {
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struct imx_mu_con_priv *cp = &priv->con_priv[i];
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cp->idx = i < 2 ? 0 : i - 2;
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@ -493,8 +521,8 @@ static void imx_mu_init_scu(struct imx_mu_priv *priv)
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"imx_mu_chan[%i-%i]", cp->type, cp->idx);
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}
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priv->mbox.num_chans = IMX_MU_SCU_CHANS;
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priv->mbox.of_xlate = imx_mu_scu_xlate;
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priv->mbox.num_chans = num_chans;
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priv->mbox.of_xlate = imx_mu_specific_xlate;
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/* Set default MU configuration */
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for (i = 0; i < IMX_MU_xCR_MAX; i++)
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@ -508,6 +536,7 @@ static int imx_mu_probe(struct platform_device *pdev)
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struct imx_mu_priv *priv;
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const struct imx_mu_dcfg *dcfg;
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int ret;
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u32 size;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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@ -528,6 +557,15 @@ static int imx_mu_probe(struct platform_device *pdev)
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return -EINVAL;
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priv->dcfg = dcfg;
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if (priv->dcfg->type & IMX_MU_V2_S4)
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size = sizeof(struct imx_s4_rpc_msg_max);
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else
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size = sizeof(struct imx_sc_rpc_msg_max);
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priv->msg = devm_kzalloc(dev, size, GFP_KERNEL);
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if (IS_ERR(priv->msg))
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return PTR_ERR(priv->msg);
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priv->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(priv->clk)) {
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if (PTR_ERR(priv->clk) != -ENOENT)
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@ -623,10 +661,21 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
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.xCR = {0x110, 0x114, 0x120, 0x128},
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};
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static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = {
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.tx = imx_mu_specific_tx,
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.rx = imx_mu_specific_rx,
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.init = imx_mu_init_specific,
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.type = IMX_MU_V2 | IMX_MU_V2_S4,
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.xTR = 0x200,
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.xRR = 0x280,
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.xSR = {0xC, 0x118, 0x124, 0x12C},
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.xCR = {0x110, 0x114, 0x120, 0x128},
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};
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static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
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.tx = imx_mu_scu_tx,
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.rx = imx_mu_scu_rx,
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.init = imx_mu_init_scu,
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.tx = imx_mu_specific_tx,
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.rx = imx_mu_specific_rx,
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.init = imx_mu_init_specific,
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.xTR = 0x0,
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.xRR = 0x10,
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.xSR = {0x20, 0x20, 0x20, 0x20},
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@ -637,6 +686,7 @@ static const struct of_device_id imx_mu_dt_ids[] = {
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{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
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{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
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{ .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
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{ .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 },
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{ .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
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{ },
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};
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20
include/linux/firmware/imx/s4.h
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20
include/linux/firmware/imx/s4.h
Normal file
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@ -0,0 +1,20 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2021 NXP
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*
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* Header file for the IPC implementation.
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*/
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#ifndef _S4_IPC_H
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#define _S4_IPC_H
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struct imx_s4_ipc;
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struct imx_s4_rpc_msg {
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uint8_t ver;
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uint8_t size;
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uint8_t cmd;
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uint8_t tag;
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} __packed;
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#endif /* _S4_IPC_H */
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