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drm/amd/pm: Add VCN reset support for SMU v13.0.6

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This commit implements VCN reset capability for SMU v13.0.6 with the following changes:

1. Added new PPSMC message ID (0x5B) for VCN reset in SMU firmware interface
2. Extended SMU capabilities to include VCN_RESET support
3. Implemented VCN reset support check:
   - Added smu_v13_0_6_reset_vcn_is_supported() function
4. Updated SMU v13.0.6 PPT functions to include VCN reset operations

v2: clean up debug info (Alex)
v3: remove unsupported message and split smu v13.0.6 changes to a separate patch (Lijo)
v4: simply the function (smu_v13_0_6_reset_vcn_is_supported) (Lijo)

Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Ruili Ji <ruiliji2@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jesse.Zhang 2025-08-13 10:40:18 +08:00 committed by Alex Deucher
parent 37b9257be7
commit 9d20f37a10
3 changed files with 12 additions and 2 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

4
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
View file

@ -94,9 +94,9 @@
#define PPSMC_MSG_RmaDueToBadPageThreshold 0x43 #define PPSMC_MSG_RmaDueToBadPageThreshold 0x43
#define PPSMC_MSG_SetThrottlingPolicy 0x44 #define PPSMC_MSG_SetThrottlingPolicy 0x44
#define PPSMC_MSG_ResetSDMA 0x4D #define PPSMC_MSG_ResetSDMA 0x4D
#define PPSMC_MSG_ResetVCN 0x4E
#define PPSMC_MSG_GetStaticMetricsTable 0x59 #define PPSMC_MSG_GetStaticMetricsTable 0x59
#define PPSMC_Message_Count 0x5A #define PPSMC_MSG_ResetVCN 0x5B
#define PPSMC_Message_Count 0x5C
//PPSMC Reset Types for driver msg argument //PPSMC Reset Types for driver msg argument
#define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET 0x1 #define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET 0x1

9
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
View file

@ -436,6 +436,9 @@ static void smu_v13_0_6_init_caps(struct smu_context *smu)
((pgm == 0) && (fw_ver >= 0x00557900)) || ((pgm == 0) && (fw_ver >= 0x00557900)) ||
((pgm == 4) && (fw_ver >= 0x4557000))) ((pgm == 4) && (fw_ver >= 0x4557000)))
smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET)); smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
if ((pgm == 4) && (fw_ver >= 0x04557100))
smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET));
} }
static void smu_v13_0_x_init_caps(struct smu_context *smu) static void smu_v13_0_x_init_caps(struct smu_context *smu)
@ -3200,6 +3203,11 @@ static int smu_v13_0_6_reset_sdma(struct smu_context *smu, uint32_t inst_mask)
return ret; return ret;
} }
static bool smu_v13_0_6_reset_vcn_is_supported(struct smu_context *smu)
{
return smu_v13_0_6_cap_supported(smu, SMU_CAP(VCN_RESET));
}
static int smu_v13_0_6_reset_vcn(struct smu_context *smu, uint32_t inst_mask) static int smu_v13_0_6_reset_vcn(struct smu_context *smu, uint32_t inst_mask)
{ {
int ret = 0; int ret = 0;
@ -3888,6 +3896,7 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
.reset_sdma = smu_v13_0_6_reset_sdma, .reset_sdma = smu_v13_0_6_reset_sdma,
.reset_sdma_is_supported = smu_v13_0_6_reset_sdma_is_supported, .reset_sdma_is_supported = smu_v13_0_6_reset_sdma_is_supported,
.dpm_reset_vcn = smu_v13_0_6_reset_vcn, .dpm_reset_vcn = smu_v13_0_6_reset_vcn,
.reset_vcn_is_supported = smu_v13_0_6_reset_vcn_is_supported,
}; };
void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu) void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)

1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
View file

@ -64,6 +64,7 @@ enum smu_v13_0_6_caps {
SMU_CAP(RMA_MSG), SMU_CAP(RMA_MSG),
SMU_CAP(ACA_SYND), SMU_CAP(ACA_SYND),
SMU_CAP(SDMA_RESET), SMU_CAP(SDMA_RESET),
SMU_CAP(VCN_RESET),
SMU_CAP(STATIC_METRICS), SMU_CAP(STATIC_METRICS),
SMU_CAP(HST_LIMIT_METRICS), SMU_CAP(HST_LIMIT_METRICS),
SMU_CAP(BOARD_VOLTAGE), SMU_CAP(BOARD_VOLTAGE),