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clocksource/drivers/timer-mediatek: Convert the driver to timer-of
Convert the driver to use the timer_of helpers. This allows to remove custom proprietary structure, factors out and simplifies the code. Signed-off-by: Stanley Chu <stanley.chu@mediatek.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This commit is contained in:
Stanley Chu
Daniel Lezcano
parent
56d52d3f56
commit
a0858f9379
1 changed files with 78 additions and 123 deletions
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@ -18,16 +18,13 @@
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqreturn.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include <linux/slab.h>
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#include "timer-of.h"
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#define TIMER_CLK_EVT (1)
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#define TIMER_CLK_SRC (2)
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@ -59,12 +56,6 @@
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#define GPT_CNT_REG(val) (0x08 + (0x10 * (val)))
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#define GPT_CMP_REG(val) (0x0C + (0x10 * (val)))
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struct mtk_clock_event_device {
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void __iomem *gpt_base;
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u32 ticks_per_jiffy;
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struct clock_event_device dev;
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};
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static void __iomem *gpt_sched_reg __read_mostly;
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static u64 notrace mtk_gpt_read_sched_clock(void)
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@ -72,36 +63,30 @@ static u64 notrace mtk_gpt_read_sched_clock(void)
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return readl_relaxed(gpt_sched_reg);
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}
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static inline struct mtk_clock_event_device *to_mtk_clk(
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struct clock_event_device *c)
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{
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return container_of(c, struct mtk_clock_event_device, dev);
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}
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static void mtk_gpt_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer)
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static void mtk_gpt_clkevt_time_stop(struct timer_of *to, u8 timer)
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{
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u32 val;
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val = readl(evt->gpt_base + GPT_CTRL_REG(timer));
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writel(val & ~GPT_CTRL_ENABLE, evt->gpt_base +
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GPT_CTRL_REG(timer));
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val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
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writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +
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GPT_CTRL_REG(timer));
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}
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static void mtk_gpt_clkevt_time_setup(struct mtk_clock_event_device *evt,
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unsigned long delay, u8 timer)
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static void mtk_gpt_clkevt_time_setup(struct timer_of *to,
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unsigned long delay, u8 timer)
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{
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writel(delay, evt->gpt_base + GPT_CMP_REG(timer));
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writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));
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}
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static void mtk_gpt_clkevt_time_start(struct mtk_clock_event_device *evt,
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bool periodic, u8 timer)
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static void mtk_gpt_clkevt_time_start(struct timer_of *to,
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bool periodic, u8 timer)
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{
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u32 val;
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/* Acknowledge interrupt */
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writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG);
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writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);
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val = readl(evt->gpt_base + GPT_CTRL_REG(timer));
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val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
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/* Clear 2 bit timer operation mode field */
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val &= ~GPT_CTRL_OP(0x3);
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@ -112,160 +97,130 @@ static void mtk_gpt_clkevt_time_start(struct mtk_clock_event_device *evt,
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val |= GPT_CTRL_OP(GPT_CTRL_OP_ONESHOT);
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writel(val | GPT_CTRL_ENABLE | GPT_CTRL_CLEAR,
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evt->gpt_base + GPT_CTRL_REG(timer));
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timer_of_base(to) + GPT_CTRL_REG(timer));
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}
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static int mtk_gpt_clkevt_shutdown(struct clock_event_device *clk)
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{
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mtk_gpt_clkevt_time_stop(to_mtk_clk(clk), TIMER_CLK_EVT);
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mtk_gpt_clkevt_time_stop(to_timer_of(clk), TIMER_CLK_EVT);
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return 0;
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}
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static int mtk_gpt_clkevt_set_periodic(struct clock_event_device *clk)
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{
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struct mtk_clock_event_device *evt = to_mtk_clk(clk);
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struct timer_of *to = to_timer_of(clk);
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mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
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mtk_gpt_clkevt_time_setup(to, to->of_clk.period, TIMER_CLK_EVT);
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mtk_gpt_clkevt_time_start(to, true, TIMER_CLK_EVT);
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mtk_gpt_clkevt_time_stop(evt, TIMER_CLK_EVT);
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mtk_gpt_clkevt_time_setup(evt, evt->ticks_per_jiffy, TIMER_CLK_EVT);
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mtk_gpt_clkevt_time_start(evt, true, TIMER_CLK_EVT);
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return 0;
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}
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static int mtk_gpt_clkevt_next_event(unsigned long event,
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struct clock_event_device *clk)
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struct clock_event_device *clk)
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{
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struct mtk_clock_event_device *evt = to_mtk_clk(clk);
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struct timer_of *to = to_timer_of(clk);
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mtk_gpt_clkevt_time_stop(evt, TIMER_CLK_EVT);
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mtk_gpt_clkevt_time_setup(evt, event, TIMER_CLK_EVT);
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mtk_gpt_clkevt_time_start(evt, false, TIMER_CLK_EVT);
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mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
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mtk_gpt_clkevt_time_setup(to, event, TIMER_CLK_EVT);
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mtk_gpt_clkevt_time_start(to, false, TIMER_CLK_EVT);
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return 0;
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}
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static irqreturn_t mtk_gpt_interrupt(int irq, void *dev_id)
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{
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struct mtk_clock_event_device *evt = dev_id;
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struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
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struct timer_of *to = to_timer_of(clkevt);
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/* Acknowledge timer0 irq */
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writel(GPT_IRQ_ACK(TIMER_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG);
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evt->dev.event_handler(&evt->dev);
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writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);
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clkevt->event_handler(clkevt);
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return IRQ_HANDLED;
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}
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static void
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__init mtk_gpt_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option)
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__init mtk_gpt_setup(struct timer_of *to, u8 timer, u8 option)
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{
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writel(GPT_CTRL_CLEAR | GPT_CTRL_DISABLE,
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evt->gpt_base + GPT_CTRL_REG(timer));
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timer_of_base(to) + GPT_CTRL_REG(timer));
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writel(GPT_CLK_SRC(GPT_CLK_SRC_SYS13M) | GPT_CLK_DIV1,
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evt->gpt_base + GPT_CLK_REG(timer));
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timer_of_base(to) + GPT_CLK_REG(timer));
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writel(0x0, evt->gpt_base + GPT_CMP_REG(timer));
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writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));
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writel(GPT_CTRL_OP(option) | GPT_CTRL_ENABLE,
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evt->gpt_base + GPT_CTRL_REG(timer));
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timer_of_base(to) + GPT_CTRL_REG(timer));
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}
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static void mtk_gpt_enable_irq(struct mtk_clock_event_device *evt, u8 timer)
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static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer)
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{
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u32 val;
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/* Disable all interrupts */
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writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG);
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writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);
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/* Acknowledge all spurious pending interrupts */
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writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG);
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writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
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val = readl(evt->gpt_base + GPT_IRQ_EN_REG);
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val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);
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writel(val | GPT_IRQ_ENABLE(timer),
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evt->gpt_base + GPT_IRQ_EN_REG);
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timer_of_base(to) + GPT_IRQ_EN_REG);
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}
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static struct timer_of to = {
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.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
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.clkevt = {
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.name = "mtk-clkevt",
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.rating = 300,
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.cpumask = cpu_possible_mask,
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},
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.of_irq = {
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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},
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};
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static int __init mtk_gpt_init(struct device_node *node)
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{
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struct mtk_clock_event_device *evt;
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struct resource res;
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unsigned long rate = 0;
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struct clk *clk;
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int ret;
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evt = kzalloc(sizeof(*evt), GFP_KERNEL);
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if (!evt)
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return -ENOMEM;
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to.clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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to.clkevt.set_state_shutdown = mtk_gpt_clkevt_shutdown;
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to.clkevt.set_state_periodic = mtk_gpt_clkevt_set_periodic;
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to.clkevt.set_state_oneshot = mtk_gpt_clkevt_shutdown;
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to.clkevt.tick_resume = mtk_gpt_clkevt_shutdown;
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to.clkevt.set_next_event = mtk_gpt_clkevt_next_event;
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to.of_irq.handler = mtk_gpt_interrupt;
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evt->dev.name = "mtk_tick";
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evt->dev.rating = 300;
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evt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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evt->dev.set_state_shutdown = mtk_gpt_clkevt_shutdown;
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evt->dev.set_state_periodic = mtk_gpt_clkevt_set_periodic;
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evt->dev.set_state_oneshot = mtk_gpt_clkevt_shutdown;
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evt->dev.tick_resume = mtk_gpt_clkevt_shutdown;
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evt->dev.set_next_event = mtk_gpt_clkevt_next_event;
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evt->dev.cpumask = cpu_possible_mask;
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evt->gpt_base = of_io_request_and_map(node, 0, "mtk-timer-gpt");
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if (IS_ERR(evt->gpt_base)) {
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pr_err("Can't get resource\n");
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goto err_kzalloc;
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}
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evt->dev.irq = irq_of_parse_and_map(node, 0);
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if (evt->dev.irq <= 0) {
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pr_err("Can't parse IRQ\n");
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goto err_mem;
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}
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_err("Can't get timer clock\n");
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goto err_irq;
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}
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if (clk_prepare_enable(clk)) {
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pr_err("Can't prepare clock\n");
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goto err_clk_put;
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}
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rate = clk_get_rate(clk);
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if (request_irq(evt->dev.irq, mtk_gpt_interrupt,
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IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) {
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pr_err("failed to setup irq %d\n", evt->dev.irq);
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goto err_clk_disable;
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}
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evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
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ret = timer_of_init(node, &to);
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if (ret)
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goto err;
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/* Configure clock source */
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mtk_gpt_setup(evt, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN);
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clocksource_mmio_init(evt->gpt_base + GPT_CNT_REG(TIMER_CLK_SRC),
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node->name, rate, 300, 32, clocksource_mmio_readl_up);
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gpt_sched_reg = evt->gpt_base + GPT_CNT_REG(TIMER_CLK_SRC);
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sched_clock_register(mtk_gpt_read_sched_clock, 32, rate);
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mtk_gpt_setup(&to, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN);
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clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC),
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node->name, timer_of_rate(&to), 300, 32,
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clocksource_mmio_readl_up);
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gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC);
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sched_clock_register(mtk_gpt_read_sched_clock, 32, timer_of_rate(&to));
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/* Configure clock event */
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mtk_gpt_setup(evt, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT);
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clockevents_config_and_register(&evt->dev, rate, TIMER_SYNC_TICKS,
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0xffffffff);
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mtk_gpt_setup(&to, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT);
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clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
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TIMER_SYNC_TICKS, 0xffffffff);
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mtk_gpt_enable_irq(evt, TIMER_CLK_EVT);
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mtk_gpt_enable_irq(&to, TIMER_CLK_EVT);
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return 0;
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err_clk_disable:
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clk_disable_unprepare(clk);
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err_clk_put:
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clk_put(clk);
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err_irq:
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irq_dispose_mapping(evt->dev.irq);
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err_mem:
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iounmap(evt->gpt_base);
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of_address_to_resource(node, 0, &res);
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release_mem_region(res.start, resource_size(&res));
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err_kzalloc:
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kfree(evt);
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return -EINVAL;
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err:
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timer_of_cleanup(&to);
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return ret;
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}
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TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);
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