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x86/asm/64: Use 32-bit XOR to zero registers
Some Intel CPUs don't recognize 64-bit XORs as zeroing idioms. Zeroing idioms don't require execution bandwidth, as they're being taken care of in the frontend (through register renaming). Use 32-bit XORs instead. Signed-off-by: Jan Beulich <jbeulich@suse.com> Cc: Alok Kataria <akataria@vmware.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Juergen Gross <jgross@suse.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: davem@davemloft.net Cc: herbert@gondor.apana.org.au Cc: pavel@ucw.cz Cc: rjw@rjwysocki.net Link: http://lkml.kernel.org/r/5B39FF1A02000078001CFB54@prv1-mh.provo.novell.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Jan Beulich
Ingo Molnar
parent
c5fcdbf155
commit
a7bea83089
13 changed files with 17 additions and 17 deletions
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@ -75,7 +75,7 @@
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* %r9
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*/
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__load_partial:
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xor %r9, %r9
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xor %r9d, %r9d
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pxor MSG, MSG
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mov LEN, %r8
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@ -66,7 +66,7 @@
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* %r9
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*/
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__load_partial:
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xor %r9, %r9
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xor %r9d, %r9d
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pxor MSG0, MSG0
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pxor MSG1, MSG1
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@ -59,7 +59,7 @@
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* %r9
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*/
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__load_partial:
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xor %r9, %r9
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xor %r9d, %r9d
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pxor MSG, MSG
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mov LEN, %r8
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@ -258,7 +258,7 @@ ALL_F: .octa 0xffffffffffffffffffffffffffffffff
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.macro GCM_INIT Iv SUBKEY AAD AADLEN
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mov \AADLEN, %r11
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mov %r11, AadLen(%arg2) # ctx_data.aad_length = aad_length
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xor %r11, %r11
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xor %r11d, %r11d
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mov %r11, InLen(%arg2) # ctx_data.in_length = 0
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mov %r11, PBlockLen(%arg2) # ctx_data.partial_block_length = 0
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mov %r11, PBlockEncKey(%arg2) # ctx_data.partial_block_enc_key = 0
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@ -286,7 +286,7 @@ ALL_F: .octa 0xffffffffffffffffffffffffffffffff
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movdqu HashKey(%arg2), %xmm13
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add %arg5, InLen(%arg2)
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xor %r11, %r11 # initialise the data pointer offset as zero
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xor %r11d, %r11d # initialise the data pointer offset as zero
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PARTIAL_BLOCK %arg3 %arg4 %arg5 %r11 %xmm8 \operation
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sub %r11, %arg5 # sub partial block data used
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@ -702,7 +702,7 @@ _no_extra_mask_1_\@:
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# GHASH computation for the last <16 Byte block
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GHASH_MUL \AAD_HASH, %xmm13, %xmm0, %xmm10, %xmm11, %xmm5, %xmm6
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xor %rax,%rax
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xor %eax, %eax
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mov %rax, PBlockLen(%arg2)
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jmp _dec_done_\@
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@ -737,7 +737,7 @@ _no_extra_mask_2_\@:
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# GHASH computation for the last <16 Byte block
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GHASH_MUL \AAD_HASH, %xmm13, %xmm0, %xmm10, %xmm11, %xmm5, %xmm6
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xor %rax,%rax
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xor %eax, %eax
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mov %rax, PBlockLen(%arg2)
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jmp _encode_done_\@
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@ -463,7 +463,7 @@ _get_AAD_rest_final\@:
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_get_AAD_done\@:
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# initialize the data pointer offset as zero
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xor %r11, %r11
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xor %r11d, %r11d
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# start AES for num_initial_blocks blocks
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mov arg5, %rax # rax = *Y0
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@ -1770,7 +1770,7 @@ _get_AAD_rest_final\@:
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_get_AAD_done\@:
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# initialize the data pointer offset as zero
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xor %r11, %r11
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xor %r11d, %r11d
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# start AES for num_initial_blocks blocks
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mov arg5, %rax # rax = *Y0
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@ -113,7 +113,7 @@ ENDPROC(__morus1280_update_zero)
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* %r9
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*/
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__load_partial:
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xor %r9, %r9
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xor %r9d, %r9d
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vpxor MSG, MSG, MSG
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mov %rcx, %r8
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@ -235,7 +235,7 @@ ENDPROC(__morus1280_update_zero)
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* %r9
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*/
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__load_partial:
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xor %r9, %r9
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xor %r9d, %r9d
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pxor MSG_LO, MSG_LO
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pxor MSG_HI, MSG_HI
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@ -113,7 +113,7 @@ ENDPROC(__morus640_update_zero)
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* %r9
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*/
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__load_partial:
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xor %r9, %r9
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xor %r9d, %r9d
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pxor MSG, MSG
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mov %rcx, %r8
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@ -96,7 +96,7 @@
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# cleanup workspace
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mov $8, %ecx
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mov %rsp, %rdi
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xor %rax, %rax
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xor %eax, %eax
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rep stosq
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mov %rbp, %rsp # deallocate workspace
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@ -235,7 +235,7 @@ ENTRY(secondary_startup_64)
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* address given in m16:64.
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*/
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pushq $.Lafter_lret # put return address on stack for unwinder
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xorq %rbp, %rbp # clear frame pointer
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xorl %ebp, %ebp # clear frame pointer
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movq initial_code(%rip), %rax
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pushq $__KERNEL_CS # set correct cs
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pushq %rax # target address in negative space
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@ -20,7 +20,7 @@ DEF_NATIVE(, mov64, "mov %rdi, %rax");
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#if defined(CONFIG_PARAVIRT_SPINLOCKS)
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DEF_NATIVE(pv_lock_ops, queued_spin_unlock, "movb $0, (%rdi)");
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DEF_NATIVE(pv_lock_ops, vcpu_is_preempted, "xor %rax, %rax");
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DEF_NATIVE(pv_lock_ops, vcpu_is_preempted, "xor %eax, %eax");
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#endif
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unsigned paravirt_patch_ident_32(void *insnbuf, unsigned len)
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@ -256,7 +256,7 @@ ENTRY(__memcpy_mcsafe)
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/* Copy successful. Return zero */
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.L_done_memcpy_trap:
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xorq %rax, %rax
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xorl %eax, %eax
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ret
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ENDPROC(__memcpy_mcsafe)
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EXPORT_SYMBOL_GPL(__memcpy_mcsafe)
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@ -137,7 +137,7 @@ ENTRY(restore_registers)
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/* Saved in save_processor_state. */
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lgdt saved_context_gdt_desc(%rax)
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xorq %rax, %rax
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xorl %eax, %eax
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/* tell the hibernation core that we've just restored the memory */
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movq %rax, in_suspend(%rip)
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