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	ALSA: hdac: Add support for hda DMA Resume capability
Skylake sports new capability of DMA resume, DRSM where we can resume the DMA. This capability is defined by presence of AZX_DRSM_CAP_ID. If this capability is present, we use this capability. So we add: snd_hdac_ext_stream_drsm_enable() - DMA resume caps snd_hdac_ext_stream_set_dpibr() - set the DMA position snd_hdac_ext_stream_set_lpib() - set the lpib Signed-off-by: Jeeja KP <jeeja.kp@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Reviewed-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Mark Brown <broonie@kernel.org>
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					 4 changed files with 100 additions and 0 deletions
				
			
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			@ -230,6 +230,15 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
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#define AZX_MLCTL_SPA			(1<<16)
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#define AZX_MLCTL_CPA			23
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/* registers for DMA Resume Capability Structure */
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#define AZX_DRSM_CAP_ID			0x5
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#define AZX_REG_DRSM_CTL		0x4
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/* Base used to calculate the iterating register offset */
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#define AZX_DRSM_BASE			0x08
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/* Interval used to calculate the iterating register offset */
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#define AZX_DRSM_INTERVAL		0x08
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/*
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 * helpers to read the stream position
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 */
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			@ -12,6 +12,7 @@
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 * @spbcap: SPIB capabilities pointer
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 * @mlcap: MultiLink capabilities pointer
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 * @gtscap: gts capabilities pointer
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 * @drsmcap: dma resume capabilities pointer
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 * @hlink_list: link list of HDA links
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 */
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struct hdac_ext_bus {
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			@ -23,6 +24,7 @@ struct hdac_ext_bus {
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	void __iomem *spbcap;
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	void __iomem *mlcap;
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	void __iomem *gtscap;
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	void __iomem *drsmcap;
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	struct list_head hlink_list;
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};
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			@ -72,6 +74,9 @@ enum hdac_ext_stream_type {
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 * @pplc_addr: processing pipe link stream pointer
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 * @spib_addr: software position in buffers stream pointer
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 * @fifo_addr: software position Max fifos stream pointer
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 * @dpibr_addr: DMA position in buffer resume pointer
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 * @dpib: DMA position in buffer
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 * @lpib: Linear position in buffer
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 * @decoupled: stream host and link is decoupled
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 * @link_locked: link is locked
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 * @link_prepared: link is prepared
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			@ -86,6 +91,10 @@ struct hdac_ext_stream {
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	void __iomem *spib_addr;
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	void __iomem *fifo_addr;
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	void __iomem *dpibr_addr;
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	u32 dpib;
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	u32 lpib;
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	bool decoupled:1;
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	bool link_locked:1;
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	bool link_prepared;
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			@ -116,6 +125,11 @@ int snd_hdac_ext_stream_set_spib(struct hdac_ext_bus *ebus,
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				 struct hdac_ext_stream *stream, u32 value);
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int snd_hdac_ext_stream_get_spbmaxfifo(struct hdac_ext_bus *ebus,
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				 struct hdac_ext_stream *stream);
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void snd_hdac_ext_stream_drsm_enable(struct hdac_ext_bus *ebus,
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				bool enable, int index);
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int snd_hdac_ext_stream_set_dpibr(struct hdac_ext_bus *ebus,
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				struct hdac_ext_stream *stream, u32 value);
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int snd_hdac_ext_stream_set_lpib(struct hdac_ext_stream *stream, u32 value);
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void snd_hdac_ext_link_stream_start(struct hdac_ext_stream *hstream);
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void snd_hdac_ext_link_stream_clear(struct hdac_ext_stream *hstream);
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			@ -77,6 +77,12 @@ int snd_hdac_ext_bus_parse_capabilities(struct hdac_ext_bus *ebus)
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			ebus->spbcap = bus->remap_addr + offset;
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			break;
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		case AZX_DRSM_CAP_ID:
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			/* DMA resume  capability found, handler function */
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			dev_dbg(bus->dev, "Found DRSM capability\n");
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			ebus->drsmcap = bus->remap_addr + offset;
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			break;
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		default:
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			dev_dbg(bus->dev, "Unknown capability %d\n", cur_cap);
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			break;
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			@ -59,6 +59,10 @@ void snd_hdac_ext_stream_init(struct hdac_ext_bus *ebus,
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					AZX_SPB_MAXFIFO;
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	}
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	if (ebus->drsmcap)
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		stream->dpibr_addr = ebus->drsmcap + AZX_DRSM_BASE +
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					AZX_DRSM_INTERVAL * idx;
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	stream->decoupled = false;
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	snd_hdac_stream_init(bus, &stream->hstream, idx, direction, tag);
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}
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			@ -497,3 +501,70 @@ void snd_hdac_ext_stop_streams(struct hdac_ext_bus *ebus)
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	}
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}
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EXPORT_SYMBOL_GPL(snd_hdac_ext_stop_streams);
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/**
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 * snd_hdac_ext_stream_drsm_enable - enable DMA resume for a stream
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 * @ebus: HD-audio ext core bus
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 * @enable: flag to enable/disable DRSM
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 * @index: stream index for which DRSM need to be enabled
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 */
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void snd_hdac_ext_stream_drsm_enable(struct hdac_ext_bus *ebus,
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				bool enable, int index)
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{
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	u32 mask = 0;
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	u32 register_mask = 0;
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	struct hdac_bus *bus = &ebus->bus;
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	if (!ebus->drsmcap) {
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		dev_err(bus->dev, "Address of DRSM capability is NULL");
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		return;
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	}
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	mask |= (1 << index);
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	register_mask = readl(ebus->drsmcap + AZX_REG_SPB_SPBFCCTL);
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	mask |= register_mask;
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	if (enable)
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		snd_hdac_updatel(ebus->drsmcap, AZX_REG_DRSM_CTL, 0, mask);
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	else
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		snd_hdac_updatel(ebus->drsmcap, AZX_REG_DRSM_CTL, mask, 0);
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}
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EXPORT_SYMBOL_GPL(snd_hdac_ext_stream_drsm_enable);
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/**
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 * snd_hdac_ext_stream_set_dpibr - sets the dpibr value of a stream
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 * @ebus: HD-audio ext core bus
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 * @stream: hdac_ext_stream
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 * @value: dpib value to set
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 */
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int snd_hdac_ext_stream_set_dpibr(struct hdac_ext_bus *ebus,
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				 struct hdac_ext_stream *stream, u32 value)
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{
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	struct hdac_bus *bus = &ebus->bus;
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	if (!ebus->drsmcap) {
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		dev_err(bus->dev, "Address of DRSM capability is NULL");
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		return -EINVAL;
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	}
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	writel(value, stream->dpibr_addr);
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	return 0;
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}
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EXPORT_SYMBOL_GPL(snd_hdac_ext_stream_set_dpibr);
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/**
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 * snd_hdac_ext_stream_set_lpib - sets the lpib value of a stream
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 * @ebus: HD-audio ext core bus
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 * @stream: hdac_ext_stream
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 * @value: lpib value to set
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 */
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int snd_hdac_ext_stream_set_lpib(struct hdac_ext_stream *stream, u32 value)
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{
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	snd_hdac_stream_writel(&stream->hstream, SD_LPIB, value);
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	return 0;
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}
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EXPORT_SYMBOL_GPL(snd_hdac_ext_stream_set_lpib);
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