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	x86/cpu, kvm: Add the NO_NESTED_DATA_BP feature
The "Processor ignores nested data breakpoints" feature was being open-coded for KVM. Add the feature to its newly introduced CPUID leaf 0x80000021 EAX proper. Signed-off-by: Kim Phillips <kim.phillips@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Acked-by: Sean Christopherson <seanjc@google.com> Link: https://lore.kernel.org/r/20230124163319.2277355-4-kim.phillips@amd.com
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					 2 changed files with 4 additions and 1 deletions
				
			
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					@ -427,6 +427,9 @@
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#define X86_FEATURE_V_TSC_AUX		(19*32+ 9) /* "" Virtual TSC_AUX */
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					#define X86_FEATURE_V_TSC_AUX		(19*32+ 9) /* "" Virtual TSC_AUX */
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#define X86_FEATURE_SME_COHERENT	(19*32+10) /* "" AMD hardware-enforced cache coherency */
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					#define X86_FEATURE_SME_COHERENT	(19*32+10) /* "" AMD hardware-enforced cache coherency */
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					/* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
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					#define X86_FEATURE_NO_NESTED_DATA_BP	(20*32+ 0) /* "" No Nested Data Breakpoints */
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/*
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					/*
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 * BUG word(s)
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					 * BUG word(s)
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 */
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					 */
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					@ -742,7 +742,7 @@ void kvm_set_cpu_caps(void)
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		F(SME_COHERENT));
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							F(SME_COHERENT));
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	kvm_cpu_cap_mask(CPUID_8000_0021_EAX,
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						kvm_cpu_cap_mask(CPUID_8000_0021_EAX,
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		BIT(0) /* NO_NESTED_DATA_BP */ |
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							F(NO_NESTED_DATA_BP) |
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		BIT(2) /* LFENCE Always serializing */ | 0 /* SmmPgCfgLock */ |
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							BIT(2) /* LFENCE Always serializing */ | 0 /* SmmPgCfgLock */ |
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		BIT(6) /* NULL_SEL_CLR_BASE */ | 0 /* PrefetchCtlMsr */
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							BIT(6) /* NULL_SEL_CLR_BASE */ | 0 /* PrefetchCtlMsr */
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	);
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						);
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